Ghislain Kaiser, CEO and Co-Founder, Docea Power

Because complexity is increasing and process nodes are shrinking, power has become a key critical issue that designers must take into account in their design flow. Most use point tools to estimate power usage when running at transistor, gate-level or register transfer level (RTL).

Battery autonomy is no longer the only driver for power management. Along with packaging and cooling costs, power consumption has become a key differentiating feature for competing devices in the marketplace.

Power and temperature are interdependent: As mobile devices integrate more features and capabilities, the more power these devices consume, and the more they heat up. The more they heat up, the more power they consume, and so on. This situation is getting worse with the next-generation nano-scale technology nodes, where the increase in power-temperature coupling due to leakage current threatens IC reliability and the risk of thermal runaway, leading to device failure. Designers have very few point tools from which to choose to address this challenge, and until now, no available tool has been capable analysing both power and temperature at the system level.

Analysing power and temperature separately late in the design cycle creates great risk to the reliability, development costs, and time-to-market for the system-on-chip (SoC). Better power and thermal predictions help designers make devices that consumers want and demand and allow them to design products in accordance with ongoing and future environmental policies.

To address the challenges of power and temperature analysis, an electronic system level (ESL) solution for modelling, simulating and optimising power and heat dissipation of electronic systems is needed.

Power and thermal effects in a SoC come from digital blocks, memory and analog blocks, and depend on power reduction techniques, how the application software runs, technology data, and so on. At this high level of complexity, the only way for designers to manage power and thermal information has been to use spreadsheets. But traditional spreadsheets have reached their limit in terms of capacity, development and maintenance. Spreadsheets also lack interoperability.

In the next 12-18 months, designers will be replacing more and more of their spreadsheets with actual EDA and ESL software tool that operates at higher levels of abstraction than RTL. System architects will better understand their designs and be able to explore their design space earlier. Because of early decisions and predictions in the design flow, power savings can reach 70-90 percent at the ESL versus 10-25% when accounted for later in the design cycle, while securing specification closure and design implementation. Replacing spreadsheets with an integrated EDA tool leads leverages the existing design flow and creates a consistent and efficient methodology for ESL to silicon, hence improving productivity.

ESL software that allows designers to model, simulate and optimise the dynamic power and thermal behavior of whole complex systems, including intellectual IP and SoC as well as boards, subsystems or any electronic device will be used by more system and specification engineers as well as software and hardware developers for mobile applications, telecommunications, gaming, automotive, consumer, medical and military systems in the next years.