Synopsys, Inc. today introduced Design Compiler® 2010, the latest RTL synthesis innovation within the Galaxy Implementation platform, which delivers a twofold speedup in the synthesis and physical implementation flow.
With this introduction Synopsys aims to achieve two important goals, one technical and one financial.

The Technical Side

It is abundantly clear that avoiding problems is more efficient than solving them. Although the design community in general has not yet shown to have fully incorporated this reality in its methods, Design Compiler 2010 appears to offer a strong tool to help designers follow the dictum. The new Synopsys tool joins products like Real Time Designer from Oasys Design Systems in allowing engineers to combine logic synthesis with place and route starting at the RTL. Following a "Think Globally, Act Locally" approach, Design Compiler 2010 provides designers with the ability of not only anticipate possible place and route problems that would result from a literal logic synthesis of RTL code, but to provide directions to avoid them before running the synthesis tool. It seems that Design Compiler 2010 is offering even more capability than Real Time Designers because it allows engineers to tailor the directives to any specific design.

Methods such as this one are a step forward because they eliminate the assumptions inherent in the more generic rules used by physical synthesis tools. Physical synthesis must follow the design rules established by the foundry with little if any knowledge of the peculiarities of the specific design. Of course, while physical synthesis tools are a good step forward over using point tools for logic synthesis and place and route, they generate what at times are very difficult problems due to design rules violations resulting from the literal application of the rules. Some of these errors can be avoided by guiding the synthesis process and thus providing more intelligence to the place and route tool. The results is less rules violations, and a time savings (read cost savings) for designers.

Design Compiler 2010 also sends an important message to designers: what you do up front determines how difficult and costly your development flow will be. Although it may be humanly impossible to predict all the problems that are inherent in a particular design, all agree that a clean and efficient system level design allows for a simpler and less costly implementation flow.

Although Design Compiler 2010 only starts at the RTL and thus not at the architectural design level, it is a step forward in increasing the level of abstraction and thus simplify the problem to be solved. There is of course a drawback. Designers used to a simpler set of rules for logic synthesis will now have to learn more about place and route, if they are to provide correct guidelines to the new tool.

The Financial Side

By incorporating place and route guidelines in Design Compiler 2010, Synopsys has significantly improved the advantage designer will enjoy when using the entire Synopsys flow, and not just Design Compiler as a point tool. The result, I expect, will be that more companies will decide to use the entire tool flow from Synopsys, instead of purchasing only licenses for Design Compiler. Thus the impact to the revenue flow should be greater than that of just new licenses for Design Compiler.

There is of course another, more profound, impact to our industry: the diminishing importance of point tools. The vast majority of startups have as their most valuable asset a new point tool which they aim to introduce in some existing design flow within some important design companies. In turn this will both gain visibility and impact the purchasing process to the extent that will cause one of the three leading EDA companies to purchase the startup.

By providing a closer integration using its own tools, Synopsys is in a leadership role in demonstrating that flow integration that allows error avoidance is more important than localized improvements. A tool that has to solve both less and simpler issues can afford to be a bit less efficient than a tool that has to solve difficult and more numerous problems. Startups, then, will need to show much greater cost savings than before in order to become viable.

More About Design Compiler 2010

To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimize iterations to speed up physical implementation. To address these challenges, topographical technology in Design Compiler 2010 is being extended to produce "physical guidance" to Synopsys' flagship place-and-route solution, IC Compiler, tightening timing and area correlation to 5 percent while speeding up IC Compiler's placement phase by 1.5 times (1.5X).

A new capability allows RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. Additionally, Design Compiler's new scalable infrastructure tuned for multicore processors yields 2X faster synthesis runtimes on four cores. These new Design Compiler 2010 productivity improvements will be highlighted by users at the Synopsys Users Group (SNUG) meeting in San Jose, California.

"Cutting design time and improving design performance are essential to keep our competitiveness in the marketplace," said Hitoshi Sugihara, department manager, DFM & Digital EDA Technology Development at Renesas Technology Corp. "With the new physical guidance extension to topographical technology we are seeing 5 percent correlation between Design Compiler and IC Compiler, up to 2X faster placement in IC Compiler and better design timing. We are adopting the new technology innovations in Design Compiler to minimize iterations while meeting our design goals in shorter timeframes."

To alleviate today's immense time-to-market pressures, Design Compiler 2010 extends topographical technology to further optimize its links with IC Compiler, tightening correlation down to 5 percent. Additional physical optimization techniques are applied during synthesis, and physical guidance is created and passed to IC Compiler, streamlining the flow and speeding up placement in IC Compiler by 1.5X. Design Compiler 2010 also provides RTL designers access to IC Compiler's floorplanning capabilities from within the synthesis environment. With the push of a button, designers can perform what-if floorplan exploration, enabling them to identify and fix floorplan issues early and achieve faster design convergence.

"For the last few years, we have used Design Compiler's Topographical technology to find and fix design issues during synthesis to give us predictable implementation," said Shih-Arn Hwang, Deputy Director R&D Center at Realtek. "We see Design Compiler 2010 synthesis results closely correlating to physical results, while accelerating placement in IC Compiler by 1.5X. This tight correlation between synthesis and layout, along with faster runtimes, is exactly what we need for reducing iterations and significantly shortening design schedules in 65 nanometer and smaller process technologies."

Design Compiler 2010 includes a new, scalable infrastructure designed to deliver significant runtime speedup on multicore compute servers. It employs an optimized scheme of distributed and multithreaded parallelization techniques, delivering an average of 2X faster runtime on quad-core compute servers while achieving zero deviation of the synthesis results.

"We've focused Design Compiler improvements on helping designers shorten design cycles and improve productivity," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "Since the introduction of topographical technology, the impact of logic synthesis on accelerating design closure with physical implementation has grown significantly. Design Compiler 2010 continues this trend, delivering a significant decrease in iterations and reducing run times in physical implementation. We have achieved this while dramatically updating our software infrastructure to best utilize the latest microprocessor architectures."

Visit Synopsys online at http://www.synopsys.com/.