A new whitepaper from Atrenta that reiterates the importance of early analysis and correction of layout problems before place and route produces issues that are more costly to address.

Any survey of chip design teams consistently points to two problem areas impacting quality and schedule of today’s system on chip (SoC) designs. Those areas are: a) completeness of verification, and b) physical design closure for area, timing and power for complex IP’s and SoC’s. With the advent of deep sub-micron technology, these problem areas have become exacerbated.

Early physical design closure is critical for successful SoC delivery. Routing congestion is one of the key aspects of physical design closure. In this paper we have focused on the logical congestion aspects. We have established the need for a solution geared towards RTL authoring and creation teams.

Some products are beginning to emerge in the EDA marketplace to tackle the congestion problem described above. SpyGlass® Physical, a new product in the Atrenta SpyGlass family, is aimed specifically toward RTL designers and offers many capabilities to resolve logical congestion issues up front, during RTL development. The product has very easy to use physical rules with debug capabilities to pin point the root cause, as well as simple reports with the congestion status of RTL blocks.

To read the white paper please go to the Atrenta page to register and choose the paper with the above title.