Mentor Graphics Corp. announced that the Catapult C Synthesis tool has been extended to support control logic and manage low power design requirements, thus enabling full-chip high-level synthesis.

This technology allows designers to use pure ANSI C++ for both algorithmic blocks and control logic blocks. Extending the Catapult C tool’s capabilities to full-chip high-level synthesis is critical due to the rapid growth in design size and complexity, which requires engineers to design hardware functionality at higher levels of abstraction.

Control logic synthesis and algorithmic synthesis have traditionally been addressed using different languages, formalisms and abstractions. The latest advances in the Catapult C Synthesis tool unifies these two domains, allowing users to describe control logic along with algorithmic behavior in a single and coherent model leveraging standard ANSI C++.

A new synthesizable C++ construct enables designers to easily specify asynchronous data communication. This mechanism allows interfacing algorithmic representations driven by the dataflow with control-dominated blocks synchronized by clocks. The result is a coding style familiar to hardware designers, letting users express communication, priority and task coordination within an abstract representation of concurrency. The new approach formalizes a modeling style, which provides the necessary accuracy for control oriented tasks, while preserving the abstraction beneficial for algorithmic subsystems.

In addition to support for control logic, the Catapult C Synthesis tool has added technology for low power design by automating two prevailing design techniques: multi-level clock gating and interfacing to dynamic power and clock management units. The Catapult C tool will analyze deep cones of logic to find gateable clocks, an otherwise error-prone and manual task typically done by backend low power experts.

To help further reduce power, the Catapult C Synthesis tool also exports real-time information on the state of all system blocks. This information is relayed to power management units leveraging dynamic frequency and voltage scaling heuristics to achieve system-wide power savings.

The synthesis process is complemented by a fully automated verification flow which for the first time lets users validate the detailed RTL-level block interactions at the C level.

The Catapult C Synthesis 2009a release is available to customers in July. The Catapult C product family ranges from $140,000 to $390,000. For more product information visit the website at http://www.mentor.com/products/esl/catapult-c.