Calypto Design Systems Inc. announced the availability of its PowerPro MG (memory gating) tool. The new tool automatically generates power-optimized RTL by taking advantage of the low-power modes available in today’s leading on-chip memories.

Employing a new "memory gating" technique, PowerPro MG eliminates manual coding. PowerPro MG will debut at this year’s Design Automation Conference (DAC) in San Francisco. Currently, the design of logic used to control low-power memory modes requires hand-coding that is time-consuming and error-prone. By automatically generating logic to control low-power modes, PowerPro MG enables the lowest-power SoC possible and reduces that portion of the design cycle from weeks to hours.

Calypto’s PowerPro MG fits seamlessly into today’s RTL synthesis flows. The tool reads in an RTL design written in VHDL or Verilog as well as the applicable memory models. Using Calypto’s patented sequential analysis technology, the tool constructs new memory gating logic that works in conjunction with the low-power memory modes to produce the lowest power memory implementation possible. Aimed at large, complex SoC designs, PowerPro MG has been proven to reduce power consumption in a variety of end applications such as storage, networking, graphics and multimedia.

Available now, Calypto’s PowerPro MG runs on PC platforms running Linux and is priced at $295K for a one year time based license. Calypto will demonstrate its new PowerPro MG product at this year’s Design Automation Conference (DAC) in booth #1610, being held July 26-31 in San Francisco. To register for a private demonstration visit: www.calypto.com/events.php.