Calypto Design Systems, Inc. announced Catapult Low-Power (LP). For those that were wondering why Mentor had given Catapult-C to Calypto, and those who having accepted the transfer were wondering what in the world Calypto would do with it, the answer arrived today in the form of a product announcement.
To begin with it is clear how Catapult-C fits with the original Calypto products. I t is a link between ESL and RTL that is parallel to the SLEC product. But the new release is much more than that. It incorporates some of the SLEC technology as well as some of the PowerPro technology, providing a HLS that is also power aware.
Catapult LP takes advantage of Calypto’s unique PowerPro technology by embedding it “under the hood” of Catapult to seamlessly minimize power RTL and optimize designs at the architecture level where 80% of power decisions are made. For the first time, Catapult LP enables designers to explore different hardware architectures and measure the power, performance and area of each solution. The net result is an ability to perform architectural refinement from an abstract C++ or SystemC model and deliver closed loop PPA optimization from high-level synthesis. Catapult LP goes beyond the architecture level by leveraging Calypto’s patented sequential analysis technology to deliver automatic fine grain clock gating. This two prong approach of optimizing the architecture followed by maximum clock gating efficiency at the register level promises the greatest power savings.
In addition to Catapult LP, Calypto is also announcing PowerPro Power Analyzer (PA) 6.0, which adds production ready power analysis. PowerPro PA provides RTL power estimation within 15% of gate level in a fraction of the time. With PowerPro PA designers can quickly estimate block-level power such as dynamic, leakage, peak, average and generate toggle activity reports. Combining PowerPro PA with Calypto's PowerPro optimization platform creates an extremely comprehensive, low-power flow across the entire SoC platform.