Cadence Design Systems, Inc. detailed the extensive expansion of its portfolio of verification IP (VIP) and memory models, which delivers a verification solution spanning silicon, SoC and system development. What is important is not only the number of VIP blocks now available, but the fact that the Verification IP can be found on the same site as the execution IP, namely the ChipEstimate site. Of course ChipEstimate has been a part of Cadence for some time now, but it has maintained its individual presence on the web, for continuity sake.
The fact that one can find both design IP and verification IP on the same site provides significant help to architects who can now choose a block not just based on its performance characteristics, but also based on the verification support existence.

The Cadence® VIP offering offers support of new protocols such as ARM® AMBA® 4 and MIPI to address early IP verification and integration through to system validation in demonstration of the EDA360 vision. In addition to memory models and VIP obtained from last year's acquisition of Denali®, complementing the metric-driven Cadence VIP, the expanded offering now supports all major third party simulators, effectively providing designers a one-stop shop of mainstream and emerging protocols for developing and verifying today's advanced electronic designs.

Specifically focused on accelerating the verification process and product delivery, Cadence's VIP Catalog covers more than 30 complex and emerging protocols and is included in an expanded VIP Catalog that features:

• Support for third-party simulators across the entire portfolio to enable all customers to deploy Cadence VIP on top of existing environments, and extended support of the Universal Verification Methodology (UVM)
• Expanded protocol availability, featuring early delivery of verification IP for emerging protocols such as the AMBA 4 specification, the latest MIPI protocols (M-PHY, DigRF and UniPro), PCI Express Gen 3, SuperSpeed USB, and Ethernet 40/100G, as well as new memory models including DDR4, LRDIMM, and Flash ONFI 3.0.
• New use models, including system validation with new accelerated VIP that addresses hardware/software integration and a new SoC Portfolio that makes SoC verification more cost effective, and a roadmap for extending the solution to enable software-driven verification, a new approach providing a programmer's view of system verification.

The overview of the new VIP Catalog, including a listing of specific protocols and new capabilities, is available at this Cadence Web site.