Cadence Releases New Digital End-to-end Flow

The fact that the EDA360 document is not just a proclamation but an active guideline for Cadence has been further underlined by Cadence's release of its new Silicon Realization flow. Silicon Realization is one of the three implementation pillars of EDA360, the other two being System Realization and SoC Realization. The fact that the company chose to connect the new release to the 28 nm process node may be a bit overreaching and in fact confusing. The problem with the association is that some of the leading foundries, such as Globalfoundries for example, see 28 nm as "simply" an optical shrink of the 32 nm process. Thus designers targeting 28 nm for Globalfoundries are actually designing using 32 nm design rules. It is obvious to me that the Silicon Realization flow, in fact, can be used with any process, although some of its features become essential when using smaller geometries.

The core of the new offering is a blend of tools and methods guided by the realization that a modern SoC comprises hardware, software, third party IP, and packaging that must integrate with the rest of the application system.

Silicon Realization offers unified design intent and verification, higher-level design abstraction, and a top-down, bottom-up methodology that fosters design convergence. Working seamlessly with Cadence’s analog/mixed-signal and silicon/package co-design domains, the new digital flow enables designers to consider the entire chip flow holistically to drive in high-performance, low-power, mixed-signal, and even 3D-IC implementations. With the new release Cadence focuses on unique and pervasive design intent, abstraction, and convergence from RTL to GDSII, then through to packaging.

The Encounter-based Silicon Realization digital end-to-end flow includes technologies such as Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Conformal technologies, Encounter Test, Encounter Timing System, Cadence QRC Extraction, Encounter Power System and Encounter DFM technologies.

Features that enhance unified intent include:

  • Complete, silicon-proven design rule intent (electrical, physical, DFM) with early, upfront tradeoff analysis, and a 2x improvement in routing runtime through intelligent via and pin-density optimizations
  • Early clock topology intent capture and planning that uses physical information to intelligently optimize clock gating and balance clock trees throughout the design during synthesis

Features that enhance abstraction include:

  • Data abstraction technologies that enable entire blocks of logic to be modeled simply and accurately, and optimized across logical and physical domains, for giga-gate scalability and design productivity
  • Support for hierarchical low-power and OpenAccess-based mixed-signal quick/detailed abstractions to enable rapid integration of IP and advanced SoCs

Faster convergence is achieved through such features as:

  • A physically aware pre-mask functional ECO capability that automates difficult to implement functional ECOs, providing faster convergence and dramatically shortening the design cycle.
  • An architecture for in-design advanced analysis that provides one-step signal integrity and timing analysis closure during the design flow for efficient design convergence
  • Accurate full mixed-signal static timing analysis and timing-driven optimization to reduce iterations between analog and digital design teams
  • And new fully-integrated 3D-IC capabilities with unified intent, abstraction, and convergence spanning digital, full-custom, and package design.

The Silicon Realization flow cannot be seen as a panacea. As with all EDA products it is a tool to be intelligently used by designers and implementers through the entire chain of command. But its premises are sound and the releases reinforces the EDA360 message of application driven implementation for EDA tools users.