The pressure to improve the verificat5ion environment is growing. Very large designs enabled by continuous advances in semiconductors manufacturing as well as the acceptance of third party IP use has increased the difficulties faced by verification engineers. Recent product releases in the emulation and acceleration market, in particular from Mentor, and virtual prototyping from Synopsys, point to increased attention on the part of EDA vendors to this market.
Cadence Design Systems, Inc is announcing a new in-circuit acceleration based on the Incisive and Palladium XP platforms for the company’s System Development Suite, extensions to the Verification IP Catalog for acceleration and emulation, and new IP targeting full system design and verification to give engineers the ability to go beyond simulation to speed verification of large-scale SoCs, sub-systems and systems.
Both the verification IP and the IP solutions aimed at NVM use in systems are a welcome sign that the technology and expertise obtained through the Denali acquisitions are not being wasted. it takes a while to assimilate a group accustomed to working in a small and fast growing company into the culture of a billion dollar company serving various markets and still recovering from serious financial difficulties.
In-Circuit Acceleration added to System Development Suite.
"The effort and cost associated with utilizing different, disconnected engines for virtual prototyping, RTL simulation, acceleration, emulation, and FPGA-based prototyping pose key challenges to delivering products on time" said Frank Schirrmeister, Senior Director, Product Marketing, System and Software Realization, who has brought his remarkable understanding of system level design to Cadence a few months ago.
Expanding upon its in-circuit emulation technology Cadence now offers as part of the System Development Suite a single heterogeneous environment for system-level verification based on the Incisive and Palladium XP platforms, which enables designers to leverage both the high speed and real-world interfaces of traditional in-circuit emulation environments combined with the analysis capabilities available in RTL simulation.
Design teams are no longer forced to create and maintain both environments, spend unnecessary time and effort to reproduce bugs, or remodel all system components targeted for one environment – tasks which are not time effective and make sub-optimal use of the existing IP assets.
New in-circuit acceleration enables teams for simulation acceleration and emulation to deploy a common unified verification environment, resulting in up-to-10x increased efficiency during system-level validation and root cause analysis. It further shortens system and SoC development times by delivering an optimal blend of performance and accuracy and optimal leverage of existing IP assets.
Verification IP (VIP) Catalog expanded for Acceleration and Emulation.
Susan Peterson Director, Product Marketing, System Realization noted that "Universal Verification Model compatible Accelerated VIP enables users to smoothly transition from simulation to acceleration, in-circuit acceleration, and in-circuit emulation, giving them the ability to verify complex Systems and SoCs that are simply too large for effective verification using traditional RTL simulation."
The Cadence VIP catalog now includes Accelerated VIP for the following interface standards: ARM’s AMBA AXI 3/4 and ACE, PCI Express 2.0/3.0, USB 3.0, 10Gb Ethernet, SATA 3, and HDMI 1.4.
New NVM Express IP Solutions
Certain computer science principles are enduring regardless of the technology used in fabricating the systems. Using a core and an operating system in a device significantly increases the need for large amount of memory. Programmers have had to deal with a shortage of memory since the first computer was built. Non Volatile Memories (NVM) are increasingly being used in SoC designs to replace rotating memories and to provide the large amount of storage required by these systems. They provide obvious advantages, including lower power consumption, better form factor, and faster read/write operations.
Cadence has introduced an IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard, an interface technology used in the rapidly growing solid-state drive (SSD) market. The solution includes Cadence Design IP for NVM Express controller and Cadence Design IP for NVM Express subsystem. The subsystem features fully-integrated component IP, including the NVM Express Controller, firmware, and the corresponding NVMe and PCIe models from the Cadence Verification IP Catalog.
NVM Express is a specification that will speed the broader adoption of PCI Express-based SSDs by improving performance and reducing power consumption and latency compared to existing SATA/SAS interfaces or proprietary PCI Express implementations. The NVM Express specification defines the register interface, command set, and feature set to provide a scalable interface for PCI Express-based SSDs.
The controller used in the Cadence NVM Express solution supports advanced command management, data tiering and hardware command acceleration. The IP is highly configurable, allowing it to target the broad scope of applications possible with NVM Express. The included driver firmware offers an easy interface to the system firmware. The solution also includes a verification and test environment spanning from the PCI Express interface to the internal bus fabric.
Cadence offers a design methodology that uses the Cadence Virtual System Platform, NVM Express and PCI Express verifications models, Cadence Incisive Software extensions and flash memory models to accelerate the design and integration of the Cadence NVM Express IP solution. These components provide a scalable verification and test platform for system-level software and hardware development and testing.