Cadence Design Systems, Inc announced major enhancements to its Virtuoso®-based custom/analog flow, boosting productivity across the entire flow from initial design specification to final GDSII and for process nodes down to 20 nanometers. The expanded custom/analog flow -- spanning design, implementation, and verification -- includes methodology improvements to help designers manage design parasitics, a DFM capability integrated within the Virtuoso environment, and the integrated Virtuoso Power System, which provides a signoff-accurate way to manage power and signal integrity issues. These enhancements, and many more, are aimed at boosting designer productivity across all process nodes.
The unified custom/analog flow offers enhancements including in-design DFM capabilities integrated within the Virtuoso environment that automatically locate and fix potential DFM violations concurrently during the design process, enabling design teams to confidently address manufacturing variability. Another significant element of the flow is the introduction of the new Cadence® Virtuoso Power System. The Virtuoso Power System provides an integrated, comprehensive, and signoff-accurate way to manage power and signal integrity issues in-design -- including IR drop and electromigration caused issues such as shorts and hotspots. And parasitic-aware design features provide early exploration of implementation effects -- such as interconnect and device parasitics, electromigration and IR drop, well proximity effects, and litho-induced variability -- thus limiting costly late-stage iterations.
New editing, estimation, and automation features help deliver unified intent, abstraction and convergence throughout the flow, essential for optimal Silicon Realization. Such new capabilities in the Virtuoso v6.1 environment enable even greater layout productivity, enhanced data-sharing around the globe, and seamless technology integration.
A new waveform viewer -- tuned for handling large transient simulation databases -- eliminates the need for design teams to buy and integrate a similar third-party tool. Other enhancements include automated constraint checking; a new design-rule editing engine designed to handle the complexity of advanced node rule sets; and an interactive short locator that guides the designer through a find-and-fix process for difficult layout-versus-schematic errors.
Finally, the Virtuoso Accelerated Parallel Simulator's new distributed SPICE capabilities extend designers' productivity for realizing design intent from specification within the Virtuoso Analog Design Environment to foundry-qualified SPICE models by harnessing the power of the latest hardware available at our customers.
The flow includes Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation technologies, Virtuoso Layout Suite, Virtuoso Power System, and Virtuoso DFM.