Cadence Design Systems, Inc. has released Encounter Digital Implementation (EDI) System 9.1, a complete and integrated digital design, implementation, and verification environment for the development of large-scale, complex SoCs. The new and expanded suite of capabilities in EDI System 9.1 aims to answer the industry call for improved designer productivity in developing advanced low power SoCs at leading-edge process nodes -- such as 32- and 28-nanometer -- with hundreds of millions of gates, including hundreds of IP elements and embedded processors.
The constant pursuit of excellence in semiconductor design leads to a stream of technology advancements and fundamental shifts in design methodologies and processes to better manage SoC complexity, improve quality of silicon, and to ensure chips get to market on time. Silicon-on-insulator (SOI), high-k metal gates, and 3D-IC/through-silicon via (TSV) are just a few examples of some of these shifts taking place. In addition, a growing list of advanced low power design techniques such as dual flip-flop, pulse latch, power switch optimization and hierarchical low power design are being explored and employed by companies seeking the utmost in power reduction. Cadence, in collaboration with leading semiconductor companies and ecosystem partners, continues to play a pivotal role in driving the definition, development, and enablement for these areas, and EDI System 9.1 is a prime example of where it all comes together.
EDI System 9.1 removes challenges to design productivity through innovative design exploration capabilities. By combining automatic floorplan synthesis, unique data abstraction modeling, and new concurrent macro- and standard cell placement, all driven by the embedded signoff analysis capabilities of EDI System, Cadence provides users the tool to find and implement the optimal physical architecture of a chip.
Design exploration does this by automatically and concurrently examining thousands of combinations of design variables, option settings, floorplan architectures, and physical implementation approaches in parallel. This exhaustive examination allows users to fully explore the range of design possibilities, and deliver smaller, faster, higher functioning chips, while accelerating design schedules.
EDI System also improves designer productivity by broadening its integrated suite of native signoff capabilities. Building on its existing foundry certified power, timing, and signal integrity (SI) signoff capabilities, EDI System 9.1 now adds silicon-accurate extraction and design-for-manufacturing (DFM) analyses to complete the picture.
The new integrated, turbo QRC extraction capability provides fast in-design, incremental signoff extraction and drives design closure for physical and electrical design requirements. Also, since foundries now mandate DFM checks in the physical design flow at 40-nanometer and below, built-in, foundry-certified DFM analysis is a must-have at these nodes. The new integrated DFM capability -- turbo Litho Physical Analyzer -- brings built-in litho pattern intelligence and filtering to the interconnect routing phase, enabling automatic detection, prevention, and correction of potential litho hotspots before they happen. This capability improves DFM and yield for advanced 40-, 32- and 28-nanometer nodes and is significantly faster than traditional lithography signoff tools.
EDI System 9.1 also extends its innovative memory architecture to achieve significant gains in memory capacity, acceleration in single-CPU operations, and improved performance scalability across its multi-CPU backplane, bringing efficient parallel processing throughout the design flow.
The convergence of design exploration, signoff-driven implementation, faster performance, and larger capacity in EDI System 9.1 has a significant impact to designer productivity. It enables designers to design, implement, and verify chips 2-3X larger and 2X faster than traditional flows and with superior quality of silicon. The tight integration of signoff checks in the implementation phase enables exceptional correlation to final silicon, thereby reducing the potential for expensive silicon respins.
More information about the company, its products, and services is available at www.cadence.com.