Cadence Design Systems, Inc. announced the addition of design intellectual property (IP) for the LPDDR3 mobile memory standard to the company's design IP portfolio. Designed to provide the high bandwidth and low power consumption required by smartphones and tablets, the Cadence LPDDR3 memory IP solution includes integrated controller and PHY support, virtual prototyping, verification IP and Allegro design-in kits to accelerate implementation and reduce design risk.

Cadence's configurable design IP allows the LPDDR3 standard to be combined with others in a single controller and PHY to enable SoCs that support multiple memory standards, making one design usable by multiple markets.

The LPDDR3 standard will offer an extension to the bandwidth of LPDDR2, reaching 6.4GByte/s per die (1600MT/s per pin) and allowing 12.8GByte/s for a dual channel configuration. It will support both PoP and discrete packaging types, allowing versatile usage. LPDDR3 will preserve the power-efficient features of LPDDR2, allowing for fast clock stop/start, low-power self-refresh, and smart array management.

As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption.