Cadence Design Systems, Inc. is offering a comprehensive suite of solutions in support of the latest DDR PHY Interface (DFI) 3.0 specification. Enabling the development of chips and systems to support the emerging DDR4 memory standard, the specification defines an interface protocol between DDR memory controllers and PHYs. Cadence supports the specification across its DDR DRAM Controller IP, DDR PHY IP, and as part of the Cadence Verification IP Catalog. Cadence introduced the industry's first DDR4 IP memory solution in April of this year.

"Our customers require DFI-compliant design and verification IP that will enable them to be first to market with next-generation SoCs that support the emerging DDR4 standard," said Marc Greenberg, director of marketing, SoC Realization, Cadence. "Our close working relationship with the DFI Technical Group ensures that we offer integration-ready DFI solutions when the specification becomes available."

DFI interface adoption continues to rise as designers seek ways to reduce the time-to-market and cost of their SoCs. Cadence has over 400 design wins for DDR controllers and PHYs, and all DDR3 designs currently in development use the DFI interface. Support for DFI 3.0 is critical to customers who must deliver solutions in support of the emerging DDR4 standard.

DFI Technical Group Releases Latest High-Speed Memory Controller and PHY Interface Specification

The DDR PHY Interface (DFI) Technical Group today released the preliminary DFI 3.0 specification, the latest version of the pervasive industry specification that defines an interface protocol between DDR memory controllers and PHYs. The new specification enables the development of chips to support the emerging DDR4 memory standard, and is the result of collaborative work between the DFI Technical Group members including ARM Limited, Cadence Design Systems, Inc., Intel Corporation, LSI Corporation, Samsung Electronics, ST-Ericsson and Synopsys, Inc. Supported by major DDR IP suppliers, the DFI interface is in use by hundreds of companies with 3100 downloads.
"DFI has quickly become the dominant interface specification for DDR controllers and PHYs, and semiconductor companies are already specifying products to support the upcoming transition to DDR4," said John MacLaren, chairman of the DFI Technical Group. "This new specification eases the integration of DDR4 memory controllers and PHYs, taking into account the complex power and performance challenges associated with implementing high-speed memory."

Building upon the solid foundation of previous DFI specifications, DFI 3.0 defines methods for interfacing to DDR4 devices with proposed data rates up to 3.2 Gbits/second per pin -- more than 50 percent faster than the current DDR3 standard -- and extends the low-power interface that was introduced with DFI 2.1. By accounting for frequency and power challenges at high speeds, the new specification helps ensure exceptional performance in systems using DDR4 memory. The preliminary specification is available now for download at www.ddr-phy.org.

About the DFI Technical Group

The DFI Technical Group is a standards organization comprised of leading semiconductor companies that implement the DFI specification. The specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, its community, activities and how to participate, visit: www.ddr-phy.org.