Since the announcement almost a year ago of the EDA360 roadmap, Cadence has been focused on developing along its lines of reasoning. Today's announcement continues the development of the SoC realization portfolio. Those who had doubts about Cadence's acquisition of Denali, most of whom predicted doom and gloom for Denali's technology, are being proven wrong by the facts. Not only is Sanjay still at Cadence, and quite satisfied there I might add, but the technology is finding appropriate places both within traditional Cadence and ChipEstimate, a portal purchased by Cadence that has retained its original branding and deals exclusively in IP for design and verification.

Given the significant impact that memory controller IP has on the overall performance of the SoC and system, Cadence is expanding the in-house development of comprehensive memory and storage controller IP to ensure maximum robustness and performance. The company plans to continue Denali's tradition of developing high-quality IP in parallel with industry standards, giving customers the ability to be first-to-market with differentiated SoC solutions. The company also plans to support its IP with a comprehensive integration environment that is unparalleled in the industry.

"We expect vendors, especially in the networking and enterprise markets, to begin designing equipment utilizing DDR4 in 2012," said Ganesh Ramamoorthy, principal research analyst, Gartner. "Since SoC designs start well in advance of system design, we believe the demand for DDR4 IP will begin from now on and grow strongly to reach peak demand by 2014."

For interface IP, Cadence will offer high-performance interface solutions, such as PCI Express Gen2 and Gen3, as well as Gibabit Ethernet (GbE), 10 GbE and 40 GbE solutions. The combined Denali and Cadence services team offers decades of design expertise, and will continue to deliver highly optimized, integrated IP solutions.

In the compute category, Cadence will continue to collaborate with leading IP providers to ensure it can support the compute needs of SoC designers. The group's primary focus will be on ensuring successful integration through advanced methodologies, tools and reference flows that take a holistic approach to SoC design and verification.

The DDR4 Solution

Cadence Design Systems, Inc. announced a comprehensive DDR4 solution that will enable SoC designers to take advantage of the performance gains afforded by the emerging DDR4 memory standard. Having worked with hundreds of customers to integrate earlier generations of this important memory controller interface, Cadence and the newly acquired Denali team offer the proven, high-quality IP and sophisticated environment required to speed integration, reduce cost and ensure design manufacturability. The solution includes hard and soft PHY IP; controller IP; memory models; verification IP; tools and methodologies; and signal integrity reference designs for the package and board.

The DDR4 specification, an evolutionary SDRAM memory technology standard currently under review at JEDEC, proposes speeds ranging from 1600 mega transfers per second (MT/s) up to 3200 MT/s, more than 50 percent faster than the current DDR3 standard. As the standard evolves to support higher frequencies and throughput, signal integrity, power and performance issues multiply. Successful IP integration hinges on both the quality of the IP and the sophistication of the integration environment. The Cadence integration environment enables customers to model and analyze their target memory topology, and verify the behavior of the IP at both the SoC and system levels.

The soft PHY and controller provide tremendous flexibility and can be synthesized to support the full range of frequencies and voltages. Designers can deliver either a pure DDR4 SoC, or combine DDR4 with other technologies like DDR3 or LPDDR2. The specification is expected to be finalized this year.

DDR4 controller IP, verification IP and memory models are available now, and supported by both Cadence and third party design tools and methodologies. A soft DDR4 PHY is expected to be available this quarter, while a hard PHY solution for 28-nm TSMC geometries is expected to be available by Q3 2011.