The new flow is a direct result of the EDA360 vision published just about one year ago. The document recognizes that systems are designed and developed based on the application they provide, not on the latest capabilities of hardware manufacturing. hardware and software components are chosen given the requirements of the application, and in the majority of cases, the software components demand the majority of the development effort, and thus are responsible for the larger share of the cost.
Although the presentation given to editors did not explicitly show co-design and co-development of hardware and software, the capabilities are inherent in the system, given existing products such as the C-to-silicon compiler HLS tool. I was told that the presentation focuses on software development and debug, yet I think that such an approach is short sighted, since the beauty of the new flow is the concurrent development and debug of the hardware and software that make up the system.
The new suite of products unveiled at industry events in Silicon Valley and Munich, Germany, promises to cut system integration time by up to half compared with previous methods for next-generation designs. The suite features four connected platforms that enable hardware-software co-design from early software development through to prototyping. The Cadence System Development Suite includes the Palladium XP Verification Computing Platform, Incisive Verification Platform and Rapid Prototyping Platform, which are available immediately; and the Virtual System Platform, currently in use with early adopters and will be widely available later this year.
"The acceleration of design complexity is even faster than we predicted a year ago, when we first discussed the disruptive transformation happening in system design," said John Bruggeman, senior vice president and CMO, Cadence. "Product development cycles are shrinking to as little as six months, putting undue pressure on design teams who must work 24/7 to deliver competitive systems – and even then there is a high risk that their designs won't see the light of day. Our suite provides a level of connection between hardware and software that hasn't existed until now and will not only enable the most efficient design methods possible, but will redefine the system design process moving forward."
The Cadence Virtual System Platform is a software development platform built on top of abstracted hardware models. It delivers an integrated and fully synchronized multi-core hardware/software debug environment, with multiple views of hardware, software, memories and registers enabling system analysis and rapid handshake between hardware and software teams. Combined with the Incisive Verification Platform, it provides a tight connection to RTL by delivering a mixed TLM/RTL unified simulator and common metric-driven verification methodology, reducing the risk of discrepancies between the abstracted hardware model and the eventual RTL. Finally, it accelerates the process of platform creation through automation by enabling customers to quickly build highly configurable transaction-level non-processors hardware models and utilize high-performance processor models delivered by third parties.
Nimish Modi, senior vice president for the System and Software Realization Group at Cadence remarked that "This integrated flow embodies the open, connected and scalable tenets of our approach to System Realization and provides a significant breakthrough in addressing the challenges of early software development and hardware/software convergence, leading to a dramatic reduction in development schedules."
The new suite is open (standards-based), connected (allowing fast migration between platforms) and scalable to meet performance, capacity and volume distribution demands.
FPGA Based Prototyping
The Cadence Rapid Prototyping Platform includes off-the-shelf FPGA boards by the Dini Group with capacities of up to 30 million ASIC gates, an integrated compile engine and multiple debug options. It supports standard ASIC flows and provides fast design mapping, multi-FPGA automatic partitioning and FPGA place and route tools. Its compatibility with the Cadence Verification Computing Platform enables migration of designs from emulation to FPGA-based prototyping. It delivers high-performance and affordable replicates for early software development and for running exhaustive regression tests while leveraging and sharing the fast bring-up times, debug capabilities and the SpeedBridge adapters' portfolio in the Cadence emulation family of products.