Cadence Design Systems has introduced a 40/100 Gigabit Ethernet (GbE) media access controller (MAC) and physical coding sub-layer (PCS) IP cores that enable the rapid deployment of SoCs for networking and high-performance computing. With more than 50 tape-outs of Ethernet designs spanning from 1 GbE up to 40 GbE, Cadence offers both the design IP and integration support required to ensure silicon success. Cadence's Ethernet solutions include unique capabilities in verification IP (VIP), emulation, virtual prototyping and silicon-package-board co-design. The design IP, including MAC and PCS, as well VIP, emulation and virtual prototyping support, are available immediately.

The Cadence 40/100 GbE MAC and PCS IP cores support the latest version of the IEEE 802.3ba-2010 Ethernet specification and sub-specifications including Energy Efficient Ethernet for power savings during idle time. The IP includes a host of configurable features such as Ethernet address match logic and frame- and priority-based flow control mechanisms for application-based customization of traffic control. In addition, a programmable inter-frame gap feature enables precise packet flow control to avoid equipment overload. Finally, the IP provides comprehensive monitoring features including error/status word for each frame that is transmitted and received; remote monitoring (RMON) and management information base (MIB) support. The 40/100 GbE MAC IP supports Gigabit media independent interfaces (XLGMII and CGMII) for connection to the attached PHY layer device, whereas the 40/100 GbE PCS IP supports integration with four/ten 10 Gigabit SerDes.