Cadence Design Systems, Inc. has announced Allegro 16.6 that it claims will accelerate timing closure for high-speed interfaces by 30-50 percent, through timing-aware physical implementation and verification delivered in the industry’s first ECAD team collaboration environment for PCB design using Microsoft® SharePoint® technology. The Allegro release 16.6 PCB solutions will be available in Q4, 2012
New features in the Allegro 16.6 product line enable enhanced miniaturization capabilities for embedding dual-sided and vertical components, timing-aware physical implementation and verification that accelerate timing closure, and improved ECAD and mechanical CAD (MCAD) co-design - all crucial for accelerating development of feature-rich electronic products.
The Allegro suite’s leading PCB design miniaturization capabilities were first introduced in 2011. The Allegro 16.6 product suite continues to leverage the latest manufacturing advances in embedding active and passive components to address the specific design requirements associated with ever shrinking board size. Components can now be embedded vertically on an inner layer of a PCB leveraging the Z-axis, which greatly reduces X- and Y-axis real estate on the board.
Allegro 16.6 accelerates timing aware physical implementation through Auto-interactive Delay Tuning (AiDT). Auto-interactive Delay Tuning lessens the time to meet timing constraints on advanced standards-based interfaces, such as DDR3, by 30-50 percent. AiDT allows users to rapidly adjust the timing of critical high-speed signals on an interface-by-interface basis, or apply it at byte-lane level, reducing the need to tune the traces on a PCB from days to hours. The EMA Timing Designer, integrated with the Allegro PCB SI capability, helps users quickly achieve timing-closure on critical high-speed signals.
PCB/enclosure co-design is streamlined through an ECAD-MCAD flow based on EDMD schema version 2.0, a proStep iViP standard. This flow reduces unnecessary iterations between ECAD and MCAD teams shortening time for product creation.
The IPC-2581 Consortium announced that consortium members have fabricated the industry’s first PCB by transferring the design data to manufacturing in the IPC-2581 format, while reducing overall fabrication time by 30 percent. This is another big step forward since the consortium validated the format earlier this year.
The bare board was fabricated with a PCB design from Fujitsu Network Communications. Fujitsu exported the fabrication data contained within a single-file of the IPC-2581 format from the Cadence® Allegro® PCB Editor. The assembly pallet was constructed and the IPC-2581 data augmented and validated using VisualCAM from WISE Software. Finally, the bare board was fabricated by CC Electronics in the UK. This 12- layer bare board is a typical optical plug-in module consisting of BGAs, QFPs and SFPs, components rotated at odd angles, a series of complex milled cutouts, the use of split planes, positive and negative plane layers, high speed nets with controlled impedance, differential pair, and matched length constraints.