The Blue Pearl Software Suite works with the Xilinx Vivado Design Suite running on Windows platforms. It includes linting, CDC analysis and automatic SDC generation. Its generated SDCs automate the synthesis and place and route phases of FPGA design implementation, and reduce iterations and overall design time. Its Visual Verification Environment makes it easy to use.
The company’s collaboration with Synopsys offers an optimized flow that works with Synopsys’
Synplify Pro FPGA synthesis software. Verilog, VHDL and SystemVerilog designers can automatically generate an exhaustive set of constraints that address false and multi-cycle paths that are compatible with Synopsys’ synthesis flow.
Blue Pearl Software, Inc. announced that it is shipping Release 6.1 of its Blue Pearl Software Suite, for Windows and Linux operating systems. The new version includes enhancements that improve and further automate the FPGA design process, including one of its biggest design bottlenecks - critical path analysis.
Enhancements to Blue Pearl Software Suite Version 6.1 include:
The new capabilities enrich the previously announced, 6.0 version. The version offered enhancements that included multi-language (SystemVerilog, VHDL, and Verilog) support, a longest path viewer, and an improved FPGA synthesis flow.
For more information, on longest path analysis read the article Find and Analyze the Longest Combinational Paths, Meet Performance Goals.