As electronics designers face increasing pressure to shorten the design cycle, the need for automatic generation of key design data increases. The penalty for missing the market window means financial losses for the company and at times, even the need to abandon that particular market. One of the ways to improve reliability and shorten development time is to increase the robustness of the relationship between RTL developers and place and route engineers. Synthesis is the key step in the process of transforming a RTL representation into a gate level one.
The manual method of writing Synopsys Design Constraints (SDC) data is often incomplete and causes a perceived need for "experimentation". Blue Pearl's product automatically generates a complete set of SDC timing exceptions significantly reducing the number of iterations for product development teams.
Shakeel Jeewoody, VP of marketing at Blue Pearl Software told me that "Blue Pearl Software assists design teams to minimize the risks of not meeting performance goals. Blue Pearl is known for its automatic Synopsys Design Constraints (SDC) generation capability, which reduces the frustrating "ping-pong" game between the Register Transfer Level (RTL) design and backend teams."
The latest release of the company's software suite allows designers to identify issues that would prevent them from meeting the design performance goals. Instead of waiting for synthesis or, even worse, place and route results, designers can use the longest path analysis feature in Blue Pearl's software suite to identify timing critical paths directly in the RTL. Front-end designers can make the required changes early in the design cycle when the design is still at the RTL stage.
The manual method requires designers to understand the synthesis process and the gate level representation. Clearly this is a method that requires more time and is more prone to errors than the one provided by the Blue Pearl suite.
Users can specify the maximum combinational levels allowed for the design or a logic block, and the tool finds paths that violate the user-specified combinational depth for a number of constraint categories. These include flop-to-flop, port-to-flop, flop-to-port and port-to-port. During the path identification phase, designers can select which end-points they are concerned with, which clock they want to limit the analysis to and what maximum fanout is allowed.
During the debug phase engineers can specify how many of a particular violation they want to see, and utilize the various filtering criteria to zoom in to a specific path of interest. Mr. Jeewoody pointed out that "Customers say that the longest path feature reduces their design cycle by weeks. Instead of multiple, long iterations in synthesis and/or place and route together with timing analysis tools, designers can use Blue Pearl's software to identify the longest timing paths."