Aldec Incorporated, an leader in front end design and verification, unveiled this week its latest verification platform Riviera-PRO 2010.06. The latest release supports the Open Verification Methodology (OVM) and the early release of the next industry standard Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities.

Riviera-PRO 2010.06 provides a pre-compiled OVM library and SystemVerilog simulator to help customers take advantage of this powerful design verification methodology to meet the challenge of verifying today’s complex designs. OVM has reached a level of maturity and stability and is the basis for the UVM assuring the long-term popularity and resulting in an increased support demand in a wide variety of tools.

Users of different levels of expertise can rely on OVM to quickly build up a layered, coverage driven, transaction-level verification environment that can be reused across different designs and different platforms. Verification engineers will appreciate the flexibility OVM gives them and hardware designers will be satisfied that they can do advanced verification without going through advanced SystemVerilog training.

Riviera-PRO 2010.06 provides a unique approach to front end design, simulation and debugging of FPGA and ASIC devices. Riviera-PRO supports the most advanced verification methodologies, including ESL, TLM, and Assertion-based verification. The product includes advanced debugging tools, code coverage and a performance waveform toolset. Riviera-PRO is a multi-platform simulator, supporting 32 and 64 bit CPU architecture, Windows® 7, Vista and XP and Linux.

Riviera-PRO 2010.06 is available today and sold directly from Aldec and its authorized world-wide distributors. For more product information or to download a free evaluation copy, visit Aldec Incorporated.