Aldec has announced ALINT™ 2010.06. The release introduces a new methodology, phase-based linting (PBL), which provides structured and prioritized phases for the analysis of HDL design issues, significantly improving development productivity and overall efficiency.

Traditional design rule checking applications analyze HDL designs against a set of hundreds of rules, leaving engineers to manage thousands of error messages from one linting session. ALINT 2010.06 provides structured and prioritized predefined flows, minimizing the number of linting iterations and error messages at each phase, and ultimately eliminating more design issues incrementally at each phase. Default phases may be modified or customized by engineers for adherence to corporate design policies or conducting targeted design rule checks.

ALINT 2010.06 is a design rule checking software solution that supports STARC (Semiconductor Technology Academic Research Center), RMM (Reuse Methodology Manual) and DO-254 “best practice” design rules that define a methodology for efficient reuse and verification of System-On-A-Chip (SoC), ASIC and large FPGAs. ALINT checks VHDL, Verilog® and mixed-language designs for structural, coding and consistency issues prior to simulation and synthesis, which can significantly reduce verification time of complex FPGA and ASIC designs.

ALINT 2010.06 is available today and sold directly from Aldec and its authorized worldwide distributors. The product offers support for STARC, RMM, DO-254 and Aldec design rule plug-ins, which are sold separately.