Aldec has introduced a low-cost Linux RTL Simulator. The new configuration supports both Linux and Windows mixed-language VHDL/Verilog simulation. Riviera-PRO LV is a multi-platform RTL and gate-level simulator that supports IEEE VHDL, Verilog and SystemVerilog IEEE standard, Xilinx SecureIP and VHDL/Verilog IP encryption. The new configuration has no limitations on ASIC or FPGA device support and includes an advanced waveform toolset and fast debugging.

Riviera-PRO LV is available today as a perpetual or time-based floating license; time-based pricing starts under $5,000 (USD). To learn more about Riviera-PRO LV, go to the Rivera Pro site.