Agnisys, Inc. a startup in Lowell, MA and New Delhi, India has come out with two new products that claim to reduce the burden on design and development teams and accelerate time to market. IDesignSpec is for development teams to create a set of documentation that drives the development process. IVerifiSpec is a verification management tool that manages requirements, features, verification plan, simulation data all in a central place.

IDesignSpec: Executable Register Specification

Few people like to write documentation, fewer still would want to maintain documentation and keep it in sync with the actual design. Yet, no one would dispute the importance of precise and accurate documentation which matches the actual implementation. IDesignSpec reverses the process. It puts the documentation at the center of the design and development process. It is a new tool and methodology that increases the productivity of FPGA/ASIC, SoC and System Design teams. It automates the generation of downstream data that typically had required manual creation from the original design specification. Its specialized editor enables designers to create correct-by-construction, reusable designs.

In a digital design process, when a single source of design information is not maintained and when design team members have to enter the same data in different ways and in different formats, it leads to inefficiencies. This not just makes the team less productive, it’s a huge time sink.

Change in the specification/register description leads to changes all over. If the change is not handled in an automated fashion, chaos reigns supreme and quality suffers.

Often the design teams overlook the importance of proper register specification and associated documentation. This leads to non-uniform specifications that are spread out all over the design environment. The specification is far removed from the real code that is implemented from them. This also leads to widespread issues with reusability and efficiency.

IDesignSpec aims to solve the problems listed above. It brings the ease of a text editor to the system architect or designer to create an “executable specification”. This specification contains everything that’s needed to fully describe the design including documentation and register descriptions. All downstream views (RTL, OVM, VMM based testbenches, IP-XACT, SystemRDL etc.) are generated from this single specification.

IDesignSpec is a Specialized Editor for Systems or SoCs (System on Chips) with intelligence about the design process. Users are spared the hassle of learning of a new language or a new GUI with their own idiosyncrasies. The tool has been purposefully designed from the ground up to be lightweight add-on to any existing design process.

The economic drivers for an efficient design process are significant. Design teams must focus on attaining system-wide design efficiency maxima. This not just takes out the drudgery of engineering and let designers focus on more creative pursuits, it also helps companies deliver defect-free products.

IVerifySpec : Closed Loop Requirement Verification

IVerifySpec is a new unifying methodology that ensures closure to Verification planning and execution. Using this methodology and enabling tools, design/verification engineers and managers have a complete handle on the verification process. In a typical flow, a verification plan is created in Excel, Word, XML etc. and replicated into the Simulation tool. As the verification process gets underway, the synchronization to the original plan is at best done manually. Further, you need help with understanding if the original requirements are being verified at all. This new methodology/tool, takes away the guessing game. In one document you describe the Verification Plan, check the latest Verification Status, know when you are done and what you are done with.

As the chip complexity grows, the need to make sure teams and resources are working towards the original requirements becomes critical. Requirement traceability is not just something that must be achieved in order to get the DO-254 certification; it is becoming a must-have methodology in order to get to market fast while using optimal resources. It shouldn’t be considered a burden, but a means to focus the team on the real objectives and get a clear understanding of where we are compared to our design verification goals.

Often times, managers and executives on the team need to know what the status of the verification work is. Where are we in terms of the Verification plan that was put together months ago? Are the requirements being verified, are we getting any closer to achieving our objectives, or is it a case of diminishing returns. This need for transparency in the verification process is crucial for managing large scale verification projects. More often than not teams report on their local achievements and the big-picture is lost in mired of statistics, fancy reports and meetings.

IVerifySpec is a new methodology that revolves around a central active design document that was put together by the Design Team. This document is used to capture all the requirements that the design team and the architects set out to implement. The Verification team refers to this document quoting specific requirements and creates a Verification Plan. The beauty of this process is that as the Design Document evolves so does the Verification Plan. The two constantly remain in sync.

The Verification plan contains the following:
· pointers to the design document detailing the requirements
· the actual coverage points as per the requirements
· details of various presumed or implemented assertions
· test benches
· details of test

As the requirements get modified the Verification Plan automatically gets the updates. Verification engineers can quickly note the changes made to the plan and evaluate effectiveness of the plan and make suitable changes. Since the latest up-to-date requirements are right there in the same document, it gives a context and an anchor point for all design and verification activities.

This methodology has many advantages, once all parties agreed to using it. It becomes a central railing point for the entire team. Any team member can see the effects of changes made to either the design or the verification plan. The team can collectively decide where more coverage or assertions are needed. New members of the team found it advantageous to quickly get up to speed about their role in the verification process. Management and executives are able to open one single document and see the status without any ambiguity and delay.

Having the requirements in close proximity to the Verification plan helps us understand the relationship between the two. This automated flow, eliminates the need to do a manual comparison of the often changing design requirements to the verification plan. In addition the close proximity of the verification results to the requirements and the plan, give a warm and fuzzy about how well the original requirements have been verified with the current effort. Any short-comings can be promptly addressed.
For further details, visit the Agnisys web site.