Agilent Technologies Inc. announced the release of its RFIC simulation, verification and analysis software -- GoldenGate version 4.4. This release offers enhanced performance, new key stability and yield analyses, and RF extensions to mixed-signal simulation. In addition, the new release brings performance and flexibility updates to its unique wireless standards-based virtual test bench capability. The new release, available this month, has a starting price of under $25,000.

"Advanced node RFIC design makes you rethink what’s important from a simulation point of view," said Paul Colestock, product planning and marketing manager with Agilent’s EEsof EDA organization. "GoldenGate version 4.4 delivers improvements for just about every important aspect of RFIC design in advanced CMOS technology nodes."

GoldenGate is part of Agilent’s RFIC simulation, analysis and verification solution that also includes Momentum for 3-D planar electromagnetic simulation, Ptolemy Wireless Test Benches for system level verification, and the Advanced Design System Data Display for advanced data analysis. This suite links the RF system, subsystem, and component-level design and analysis as part of a unique and comprehensive RFIC design flow. GoldenGate is fully compatible with Cadence IC5 and IC6 platforms.

Two specific areas that have been significantly improved with this release are design analysis and design verification.
Design Analysis:

• Performance Enhancements: Improvements in periodic steady state (Harmonic Balance) performance allows verification in half the time without loss of accuracy or convergence. Other enhancements accelerate Noise analysis as well as Fast Envelope support for Ptolemy wireless test benches
• Fast Yield Contributor: improve yield by optimizing only what really matters. Determine device, circuit and block yield contributions at any stage of the RFIC design flow
• Periodic Steady State (Harmonic Balance) based Stability Analysis: improve the stability of oscillators and driven RF circuits with large signal black box Nyquist and Eigenvalue stability analysis
• New modeling option for dispersive components in Envelope Transient: more accurately predict the effect of dispersive S-parameter and transmission lines included in Envelope simulations

Design Verification:

• Comprehensive Wireless Test Benches for GoldenGate: leverage Agilent’s Wireless Verification IP to verify RF designs to standards based or custom specifications with new Ptolemy wireless test bench export capability for GoldenGate
• Envelope-AMS simulation with GoldenGate: Simplify adding digital and mixed signal components to traditional RF analysis
• RF passive component library with over 150 additional components: verify RFICs with package and board level RF passives using an expanded ADS passive RF component library for GoldenGate
• Parallel Sweep Tasks: in addition to Monte-Carlo and Corner Analysis, GoldenGates cost effective parallel licensing option has been extended to also support parallel sweep tasks

Additional Features

GoldenGate 4.4.0 delivers improvements for just about every important aspect of RFIC design in advanced silicon and CMOS technology nodes. It delivers major enhancements in the key analyses and verification flows that designers need not only to improve the performance and yield of their RFICs, but also their productivity.

New Fast Yield Contributor Analysis
While statistical Monte-Carlo analysis for performance verification and yield has improved in recent years with the addition of advanced sampling techniques, boundary modes for corner analysis etc, it has not proven to be a tool that designers use every day for circuit and block level design. The primary reasons are that standard statistical Monte-Carlo trials still take too long to complete and that results cannot easily give insight into what is causing the variability in the design. On the other hand, if relegated as a technique for final verification only, its potential impact on improving the performance yield is diminished. In order to unlock the real potential of statistical Monte-Carlo at all phases of the RFIC design flow, Agilent has developed a new Monte-Carlo like analysis technique that is fast, accurate, and that can determine the device, circuit, and block level contributors to performance variation in any phase of the design flow. Fast Yield Contributor analysis allows the designer to optimize at the circuit, block, and functional path level with an understanding of key underlying contributors and their correlation and statistical impact on overall performance.

Periodic Steady State (Harmonic Balance) Based Stability Analysis
The use of high Ft devices in advanced silicon and CMOS technology nodes for RFIC design can pose new problems related to circuit stability. While there are many techniques available to analyze the stability of RF circuits, most rely on DC, small signal s-parameter analysis, or transient analysis to provide insight into potential oscillations. Many of these are small signal and can be performed relatively quickly. Transient analysis however, the primary way to analyze large signal effects, can require long simulation times and complex and time consuming user interaction to determine the actual oscillation frequencies. To eliminate these barriers and provide a real tool for large signal stability analysis in advanced technology nodes, GoldenGate 440 introduces periodic steady state (Harmonic Balance) based Nyquist and Eigenvalue stability analyses. The large signal black box stability of oscillators and driven RF and high speed circuits can now be analyzed under real signal conditions in a fraction of the time even for the largest circuits including parasitics.

Comprehensive Wireless Test Benches for GoldenGate
Wireless communication systems continue getting more complicated with the release of each new standard. Systems engineers and RF IC designers need to collaborate more than ever on specifications driven verification. Agilent is uniquely positioned to leverage the power of the Ptolemy Systems Simulator and our comprehensive library of standards based wireless verification IP for RFIC design and verification in the Cadence Virtuoso based design flow. Our approach allows the Systems Engineer to use their expertise to configure and package wireless verification test bench libraries for the RFIC Designer to use these in a manner appropriate for IC level design. These verification test bench libraries consist of the appropriate simulator settings, standards based or custom complex modulated RF or baseband sources, baseband algorithmic data processing sinks and Data Display visualization templates. There are over a dozen wireless verification IP libraries available covering cellular, mobile broadband, digital TV, and wireless video standards and their variants. The RFIC designer can use these wireless verification test bench libraries as "Virtual Test Benches" in GoldenGate without modifying the designers golden schematic. Applications include any wireless design with RF to RF, RF to Baseband, Baseband to Baseband, or Baseband to RF signal configurations. This improved link between the RF Systems Engineer and RFIC Designer streamlines use of systems level verification IP during the RFIC design flow and lets each expert work in their own domain but still share vital information.