Accellera Works Toward a Unified Verification Methodology (UVM)

Accellera believes that the release of its UVM document is only a couple of months away. Can this really be true?

Design verification, in all of its various stages, continues to be a costly and challenging task, in spite of efforts dating back to the 1980s to provide engineers with better design tools. A quarter of a century after the introduction of Verilog and VHDL, languages meant to simplify the description of a design and thus ease the verification burden, costs continue to rise. Silicon respins due to design errors not only have not diminished in number, they have actually increased. This is an indication that complexity has grown more than the ability of verification tools to detect errors.

EDA tools developers have known for some time that not only tools need to be improved, but design methods also need to become more verification aware. So, in the usual highly competitive manner the EDA industry loves, a couple of years ago Cadence and Mentor agreed to develop together a verification methodology for SystemVerilog and called it: OVM which stands for Open Verification Methodology. Of course the word "open" in EDA does not mean freely available and thus Synopsys, who felt excluded from such "openness", insisted with VMM which stands for Verification Methodology Manual. VMM development started as early as 2005 when Synopsys partnered with ARM on the project. So one can safely state that OVM was a response to the lack of "openess" on the part of Synopsys toward allowing the other big two in the game without a price (and why should they?). How provincial EDA must seem to our major users! As you can imagine EDA customers were thrilled at the prospect of another war similar to the Verilog/VHDL wars of twenty or so years ago.

Accellera, the industry standard organization who has demonstrated a willingness to go where no one has gone before, acknowledged the problem and started a Technical Subcommittee with the aim of developing a unified methodology, called UVM, for Unified Verification Methodology.

As the year 2009 was coming to a close, the Technical Subcommittee (TS), at the prodding of "the elephant in the room" that answers to the name of Intel, reached a breakthrough, or so it seems, when Cadence, Mentor, and Synopsys agreed to begin a focused technical work project aimed at unifying the two methodologies. Some of the marketing representatives at Synopsys and Cadence have told me they expect the release of UVM in March this year. As should be expected the unrestrained joy in the streets of the silicon designers and providers should be restrained by appropriate skepticism..

The Details Make Things Difficult

As with every engineering task, the details are getting in the way of rapid progress. To begin with, the agreement was reached by a majority vote, meaning that not everyone was in favor of the motion as written. The problem, according to Mentor is in the timing. The present version of OVM is 2.0.3. It seems that OVM 2.1 was only a week or so away from being released. Yet, according to Synopsys, it is OVM 2.0.3 the version that will be used as the basis for the TS work. Mentor is pointing out the obvious: why disregard the work done to develop the 2.1 version?

Synopsys says that "We need to start with something and build on it. As a base OVM 2.0.3 will serve to create more features and improve users productivity". So, what is new in OVM 2.1 is not discarded a priori, it is just up for review. But when you ask Cadence which version of OVM will be used to create UVM, they say OVM 2.1, because it is released and it does not make sense to go back. Tom Anderson, Product Marketing Director for Verification Software at Cadence expects that OVM world, the association of OVM users, will continue to exist and that it will concern itself with both OVM and UVM topics.

One of the aspects of this work that holds positive, yet unexpected, outcome is that UVM will need to fully harmonize with the TLM specification from OSCI. Although there are many common members of the two organizations, there has never been a formal, structured, cooperation method between Accellera and OSCI. The development of UVM might give both Accellera and OSCI a real opportunity to put together a structure aimed at harmonizing each other's work, to the significant benefit of the EDA industry.

From a political point of view, the person that should be the principal architect of UVM is also a significant obstacle to speedy progress. Janick Bergeron, the architect of VMM, is a well known SystemVerilog and verification expert, and happens to be a Synopsys employee. Since the aim is to take OVM as the base and enrich it with VMM features, Cadence and Mentor expect that the chief architect will be someone who is intimately familiar with OVM, and that person is not Janick.

The final hurdle I am aware of is the matter of the license. OVM is distributed as open source under the Apache style license. Accellera has never developed a standard that is open source, it kind of runs against the idea of "standard". There seems to be significant belief within the interested parties that such issues are manageable. To begin with the matter of what is standard in an open source environment can be easily handled. What Accellera will release is the standard. People are free to add to it but not modify it under the open source environment. The additions will then be considered for inclusion in a later version of the standard. This seems to be a minor problem.

What Will Make the Job Easier

In most cases, like when you need to develop a language or a format, the standard needs to be firmly adhered to and no changes can be tolerated. But OVM, VMM and thus UVM are libraries, and so it is possible to have a standard base library and not only additional capabilities contributed by the open source community, but also OVM and VMM features that would have been deprecated (made obsolete) by the standard, and which are used by customers, that do not survive the merger.

Cadence, Mentor, and Synopsys all have major customers that, just like Intel, need a unified methodology. Here money talks loud and thus the desire of the three vendors to satisfy their customers is great. It must be noticed that the vote to start UVM came at the end of a fiscal quarter, a time when license renewals are discussed with great attention.

Finally no one has suggested forming yet another consortium to get the job done. Accellera has, with the exception of the IEEE, the best experience in EDA in developing lasting standards that span the gamut of all EDA market segments. The job will get done, the standard will be robust, and if not by March, it will be here by June, in time for DAC.


OVM and Openness

Yes Tom from Cadence is correct. MY bad. What I meant to say was that the development of OVM was not truly open. Cadence and Mentor developed OVM without Synopsys. And, according to Synopsys, VMM predates OVM. Thus the conflict, something definately not unusual in EDA.
Gabe Moretti

OVM is truly open

Gabe, thanks for your comprehensive summary of the Accellera UVM effort and its decision to use the OVM as the base. However, I was confused by your statement that 'the word "open" in EDA does not mean freely available and thus Synopsys, who felt excluded from such "openness"...' There are certainly examples in EDA where the word "open" is used rather euphemistically, but the OVM is truly open. Every version is released as open source under Apache; there is nothing more open than that. OVM is and has always been freely available to Synopsys or anyone else.