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IP Cores

Tensilica Introduces Third Generation Diamond Standard Controllers

Mon, 2010-03-15 11:01 — Gabe Moretti

Tensilica, Inc. has announced the immediate availability of its third generation of this family of products. The five upward-compatible processor cores are based on the company's common Xtensa architecture and provide the price/performance/low-power required for a wide range of embedded control functions in today's compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15 percent faster clock speed, up to 20 percent smaller die area and up to 15 percent less power consumption Tensilica stated.

Evatronix To Offer Free Technical 8051 And USB Seminars

Thu, 2010-03-11 14:58 — Gabe Moretti

Evatronix SA, announced a series of free technical seminars on two of the most popular IP technologies – 8051 and USB – taking place in China and Taiwan – Beijing (March 25) and Hsinchu (March 30), respectively.

"We are excited about this opportunity to share the 13 years of our IP design and integration experience with every engineer involved in the SoC development process," said Michal Jedrak, Technical Marketing Manager at Evatronix. "Our seminars offer an excellent chance to discuss the hottest ASIC and FPGA design topics and get immediate answers to key questions."

Carbon Unveils New Generation of ARM Models with Availability of Mali Models

Mon, 2010-03-08 15:57 — Gabe Moretti

Carbon Design Systems announced the availability of virtual models for ARM Mali Graphic Processor Units (GPUs). These new models, including the Mali-200 and Mali-400MP, are compiled directly from the ARM register transfer level (RTL) code and are 100% implementation accurate.

Forte Design Systems Ships Latest Version of CellMath Designer

Fri, 2010-03-05 09:40 — Gabe Moretti

Forte Design Systems, announced it is shipping the latest version of CellMath Designer datapath synthesis and Cellmath IP software. The CellMath family allows register transfer level (RTL) designers to reduce area, improve performance and lower power consumption for their existing datapath-intensive design blocks.

CoWare Releases Renesas' SH-4A Core Model and Reference Virtual Platform

Tue, 2010-02-16 10:51 — Gabe Moretti

CoWare Inc., a company in the process of being acquired by Synopsys, announced the availability of a high-speed model for Renesas Technology’s (Renesas) SH-4A core model. The model has been developed in collaboration between CoWare and Renesas to ensure the highest level of quality and was verified using Renesas’ test suite. The model is already in use at Renesas for the creation of high-speed virtual platforms targeted at customers in the automotive, consumer, and wireless markets.

Carbon Design Systems, VeriSilicon Form IP Partnership

Fri, 2010-02-12 09:55 — Gabe Moretti

Carbon Design Systems and VeriSilicon announced that they have partnered to integrate VeriSilicon’s ZSP models into the Carbon SoC Designer virtual platform. Processors from VeriSilicon are fully integrated with SoC (system on chip) Designer and enable users to perform implementation-accurate architectural analysis and pre-silicon firmware development.

Tensilica Introduces HiFi EP DSP Core

Wed, 2010-02-03 12:03 — Gabe Moretti

Building on the success of its HiFi 2 Audio DSP (digital signal processing), Tensilica has introduced HiFi EP, a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. It has also been enhanced for very efficient, high-quality voice pre- and post-processing. These enhancements result in up to 40 percent lower power and up to a 50 percent size reduction.

Synopsys Acquires VaST Systems Technology Corporation

Wed, 2010-02-03 11:38 — Gabe Moretti

Synopsys, Inc. has acquired VaST Systems Technology Corporation to extend its virtual prototyping solutions into the automotive and consumer application space. The acquisition adds a comprehensive set of processor sub-system models frequently found in automotive and consumer applications to Synopsys' virtual prototyping portfolio. Processor sub-system models allow developers to accelerate the virtualization of electronic systems and to start software development nine to 12 months prior to the availability of silicon.

Evatronix And CMP To Provide Universities And Research Labs With Advanced IPs

Mon, 2010-02-01 20:52 — Gabe Moretti

Evatronix SA and Circuits Multi Projects (CMP), today announced their collaboration and development of an educational program by including the distribution of the large portfolio of Evatronix Intellectual Property (IP) for Universities and Research Laboratories.

Virage Logic’s 45nm and 28nm SiWare Memory Compilers Support Calypto’s PowerPro MG tool

Mon, 2010-02-01 20:16 — Gabe Moretti

Calypto Design Systems Inc. announced that Virage Logic’s 45-nanometer (nm) and 28nm SiWare Memory compilers now automatically generate PowerPro MG power optimization models for reducing System-on-Chip (SoC) embedded memory power. This support is the result of a collaboration between the two companies to reduce on-chip SoC memory power. Using PowerPro MG, designers can reduce both dynamic and leakage power, resulting in up to 80 percent memory power reduction compared to previous implementations.