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Cadence Expands NAND Flash Design IP Offering With ONFI 3 PHY and Controller

Mon, 2012-01-09 17:47 — Gabe Moretti

It is undeniable that as software gains a larger role in system design and implementation high speed memory will become essential. But the memory block itself must be supported with the highest possible data transfer rate or a bottleneck occurs and advances in memory structure become irrelevant. I have been waiting for a signal from Cadence that its acquisition of Denali would add a significant contribution to the bottom line. Today's announcement is such proof. Cadence has brought together IP modeling, IP construction, and IP verification all in an offering that allows designers to take full advantage of the leading standard in data transmission protocol.

Cadence Expands Verification IP Portfolio Supporting Emerging Mobile Standards

Wed, 2011-09-28 13:49 — Gabe Moretti

Through close collaboration with leading system and semiconductor companies, and standards bodies, Cadence is delivering VIP at an early stage.

Cadence Announces DFI 3.0-Compliant Design and Verification IP

Wed, 2011-09-21 14:40 — Gabe Moretti

Cadence Design Systems, Inc. is offering a comprehensive suite of solutions in support of the latest DDR PHY Interface (DFI) 3.0 specification. Enabling the development of chips and systems to support the emerging DDR4 memory standard, the specification defines an interface protocol between DDR memory controllers and PHYs. Cadence supports the specification across its DDR DRAM Controller IP, DDR PHY IP, and as part of the Cadence Verification IP Catalog. Cadence introduced the industry's first DDR4 IP memory solution in April of this year.

Synopsys Announces Availability of Reprogrammable Non-Volatile Memory IP

Mon, 2011-06-27 15:45 — Gabe Moretti

Software, really firmware, represents an increasing share of IC designs. Therefore memory importance is increasing, and reprogrammable non-volatile memory grows in importance even more. Synopsys has announced the immediate availability of DesignWare® AEON® Non-Volatile Memory (NVM) IP for multiple 180-nanometer (nm) process technologies. The complete specification of the product can be found here.

SoCIP Technology Conference In China

Fri, 2011-06-24 07:59 — Gabe Moretti

Underlying, if needed, the growing importance of the Chinese market, S2C Inc has been organizing conferences and seminars in China. Since its founding in 2003, S2C has been focused on delivering design and verification tools, silicon IP, and SoC design services to the greater China market.

Kilopass Introduces Industry's First Embedded Multi-Time Programmable Non-Volatile Memory in 40nm Logic CMOS

Wed, 2011-04-20 08:27 — administrator

Kilopass Technology Inc. introduced Itera, the industry's first and only embedded multi-time programmable (MTP) NVM in 40nm, during the Linley Tech Mobile Conference. The company states that using Itera, system-on-chip (SoC) designers can achieve significantly lower costs (70% less), higher performance (24X increase), and improved integration by replacing external serial EEPROM and NOR flash in high-volume mobile and consumer applications. Implemented in standard CMOS with no additional process steps or wafer process adders, Itera provides up to 1 megabit (Mb) of storage capacity and 1024 cycles of re-programmability in applications such as time stamp, key revocation, firmware updates, and trimming adjustments.

Cadence Announces Availability of DDR4 IP Solution

Mon, 2011-04-11 15:20 — Gabe Moretti

Since the announcement almost a year ago of the EDA360 roadmap, Cadence has been focused on developing along its lines of reasoning. Today's announcement continues the development of the SoC realization portfolio. Those who had doubts about Cadence's acquisition of Denali, most of whom predicted doom and gloom for Denali's technology, are being proven wrong by the facts. Not only is Sanjay still at Cadence, and quite satisfied there I might add, but the technology is finding appropriate places both within traditional Cadence and ChipEstimate, a portal purchased by Cadence that has retained its original branding and deals exclusively in IP for design and verification.

Cadence Releases Wide I/O Memory Controller IP Solution

Mon, 2011-03-28 07:54 — Gabe Moretti

Cadence Design Systems, Inc.announced that it is first to market with a licensable, wide I/O memory controller core, along with an integration environment, that brings PC-like performance to mobile applications like smartphones and tablets. Enabling up to four times the performance of conventional memory interfaces, the Cadence wide I/O interface not only meets the performance metrics of the proposed specification, but includes unique optimizations such as traffic reordering and several low-power features that lead to better overall system operation.

Complemented by memory models, verification IP (VIP) and a 3D IC design methodology, the wide I/O IP lowers the risk and overall cost of SoC design.

Freescale Licenses Synopsys' DesignWare IP Portfolio to Accelerate SoC Designs

Wed, 2011-03-23 08:58 — Gabe Moretti

The fact that advanced semiconductor processes require closer relationships between the foundry and the IP provider found further confirmation with Freescale licensing of Synopsys' IP portfolio for SoC designs. Although it is likely that the agreement will benefit designers targeting the 40nm process, it makes much more viable using the 32 and 20 nm processes. It is becoming obvious that at 20 nm designers will have to use only IP that has been pre-certified by the foundry.

Interoperable IP Delivery

Thu, 2011-03-10 09:29 — administrator

By Jaroslaw Kaczynski, ALDEC

The paper describes the theoretical background, current status and future challenges facing interoperable cryptosystem for safe delivery of Intellectual Property (IP) to be used in VHDL and SystemVerilog design and verification. The system must be reliable, and interoperable, i.e. enable safe use of IP source in a variety of tools. IEEE P1735 Working Group currently develops proposed standard describing such a cryptosystem.