In a move reminiscent of the style of Carl Icahn, Mentor lowered its costs by exchanging Catapult C with stock of Calypto. In this manner no money exchanged hands and Mentor lowered its development and maintenance costs in the very competitive area of High Level Synthesis (HLS). The move came as a surprise to those involved in the Catapult C project. Simon Block, even a couple of weeks ago had agreed to submit an article about the product for the August issue of Assembling The Future newsletter.
Mentor Graphics Corporation has been focused on embedded systems development for some time. It has announced a new program composed of the Mentor® Embedded professional services and products specifically for hardware companies. The Mentor Embedded Hardware Enablement Program provides a spectrum of comprehensive services and training for embedded Android, Linux®, open source tools (GNU, GCC, Eclipse), user interface (UI) creation, and vertical markets, including in-vehicle infotainment (IVI), smart energy and retail applications.
Synopsys, Inc. is pursuing its expansion into non-traditional EDA markets. These markets are all related to EDA in the sense that they address systems that contain electronic components built using traditional EDA tools. The corporation shows to be very focused to provide system solutions to its customers that span design, development and production of complete systems.
Synopsys has released a new prototyping environment that combines technology from Virtio, Coware, and Vast. When the Virtio acquisition was announced in May of 2006, few if any would have stated that the acquisition was the first step in the implementation of a long range plan. Five years plans, and possibly longer, that are actually implemented are extremely rare in EDA. And yet, last year the company acquired CoWare, another company with technology closely related to virtual prototyping, and Vast Systems, a company with IP that is used by many automotive company around the world.
All is left is to wait and see how the Virage Logic acquisition will fit in the virtual prototyping market: I have ideas, but they are not for free.
The new flow is a direct result of the EDA360 vision published just about one year ago. The document recognizes that systems are designed and developed based on the application they provide, not on the latest capabilities of hardware manufacturing. hardware and software components are chosen given the requirements of the application, and in the majority of cases, the software components demand the majority of the development effort, and thus are responsible for the larger share of the cost.
Over the years, the semiconductor industry has been using C/C++ high-level synthesis (HLS) tools as one way to address the complexity of implementation and verification of hardware acceleration cores due to the growing complexity of standards in video, imaging, wireless, and other multimedia and communications applications. However, these challenges have limited the adoption and scalability of these tools. This paper will discuss some of these challenges and introduce Synphony C Compiler (SCC), a new high-level synthesis product from Synopsys that includes some unique and effective technologies that address the challenges in high-level synthesis adoption.
Synopsys took two major steps in the prototyping market segment during DVCon. First it released a new prototyping board, the HAPS-600 and then, the following day, it announced the release, in collaboration with Xilinx, of a FPGA-Based Prototyping Methodology Manual(FPMM). The product and the manual complement the family of virtual prototyping tools that Synopsys already offers. Thus software developers are now supported through the entire life of a prototype, enhancing the ability to develop embedded software in parallel with the SoC hardware. Synopsys plans to create a community of practicing prototyping engineers and users around the book.
Synopsys, Inc. announced the broad availability of Platform Architect with Multicore Optimization Technology, a new solution for performance analysis and early definition of multicore system architectures in SystemC. Using Platform Architect with Multicore Optimization Technology, designers of SoCs, chipsets and systems can capture hardware/software performance models of multicore system architectures in the early concept phase for robust performance measurement and trade-off analysis prior to software availability.
Cadence Design Systems, Inc. announced that Andes Technology, a Taiwanese provider of high-performance, low-power 32-bit processor IP and SoC platforms, has adopted the Cadence® digital front-end low-power design flow. The flow, based on the Common Power Format (CPF), deploys Cadence synthesis, simulation and formal verification technology. It enables Andes to provide its customers a scalable and configurable low-power management framework that blends hardware and software solutions for sophisticated power domain partitio ns and power scaling schemes.
Mentor Graphics Corp. announced that Toshiba Information Systems (JAPAN) Corporation has expanded their adoption and deployment of the Catapult® C tool for the high-level synthesis (HLS) of next generation application specific integrated circuits (ASICs) for audio, communication and image processing systems.