Yesterday I spent some time with Eric Lish, the Chair of OSCI. Eric is an Intel veteran, having spent 21 years, and counting, with "the other big blue" company. At present he manages the Virtual Platform Center of Excellence in Chandler Arizona.

In discussing OSCI's past achievements and future plans it became clear to me that if one had to identify the single most important contribution the consortium has made to EDA, one would have to choose TLM. Transaction Level Modeling was not a new concept before OSCI turned its attention to it. VHDL, in fact, the greatly misunderstood and poorly marketed language, can in fact be used for architectural exploration and modeling at the transaction level. But that is mostly water under the bridge, and there was the need to open the possibility of real architectural design in another environment, free of the legacy of the past.

Jasper Design Automation announced the availability of Proof Kits for LPDDR1 and LPDDR2, and DDR3 SDRAM. The Kits are sets of properties, written in SystemVerilog, related to standard JEDEC interface protocols. Each Proof Kit includes a Formal Testplan providing detailed instructions on verifying DDR designs, plus properties for the protocol that the JasperGold Verification System can prove against designs employing the standard. LPDDR solutions are experiencing high growth in mobile and embedded markets as demand for the low-power parts surges.

OneSpin Solutions announced the customizable integration between OneSpin’s 360 MV formal assertion-based verification (ABV) solution and Platform Computing’s LSF infrastructure. The integration enables 360 MV users to distribute assertion proofs onto multiple heterogeneous computers.

The customizable integration between 360 MV and Platform LSF allows users to adapt job scheduling and resource utilization to their needs. Users can track named proof tasks using LSF monitoring tools, which report progress directly into the 360 MV graphical environment.

Calypto Design Systems Inc. announced that Virage Logic’s 45-nanometer (nm) and 28nm SiWare Memory compilers now automatically generate PowerPro MG power optimization models for reducing System-on-Chip (SoC) embedded memory power. This support is the result of a collaboration between the two companies to reduce on-chip SoC memory power. Using PowerPro MG, designers can reduce both dynamic and leakage power, resulting in up to 80 percent memory power reduction compared to previous implementations.