DAC Keynotes Announced

This week’s big news is that Design Automation Conference keynotes have finally been announced, with only seven weeks to go until the doors open at the San Diego Convention Center.   

The week starts with “Up Close and Personal with Steve Wozniak” Monday, June 6, from 2-3pm.  Wozniak, founder of Apple Computer and chief scientist for Fusion-IO, will be hosted by Magma and interviewed by San Jose Mercury News Columnist Mike Cassidy.  Wozniak will provide insight into the vision that started the largest and most successful technology company, and will cover a wide range of topics, including the joy of engineering and converting innovative ideas into reality.  

Lisa Su, Freescale Semiconductor’s senior vice president and general manager of Networking and Multimedia, will offer a look at “Megatrends Driving Embedded Multicore Innovation” Tuesday, June 7, from 8:30-10am.  Dr. Su will outline the evolution of embedded multicore processing solutions that enable growth in the mobile device and infrastructure markets.  She will address the evolution of the network infrastructure, growth of multi-purpose embedded devices, the trend toward heterogeneous SoC integration, balanced by market realities of maintaining system development costs and energy efficiency.  

Wednesday, June 8, Gadi Singer, Intel’s vice president of the Intel Architecture Group and general manager of the SoC Enabling Group, will discuss “The Imminent EDA Transformation” from 11am-noon.  He will describe why the EDA industry faces a substantial shift as electronic systems go through fundamental and rapid change in TV, in-vehicle devices, phone, tablet and PC domains.  According to Singer, these new systems require unprecedented connectivity, hardware and software complexity, and application and user interactions.  To meet these challenges, Singer believes that the EDA industry must evolve and expand to enable interdependent silicon, software, system and experience solutions.  

And finally, Dharmendra S. Modha, founding manager of the Cognitive Computing group at IBM’s Almaden Research Center, will address the DAC audience with a presentation on “Cognitive Computing:  Neuroscience, Supercomputing, Nanotechnology” Thursday, June 9, from 11am-noon.  He will detail the goal of the DARPA SyNAPSE project to build brain-like cognitive computing chips that scale to human cortex by moving beyond the von Neumann architecture and become the brains behind IBM’s Smarter Planet vision. 

More information at:  www.dac.com  

Deep Chip’s  “Two stories Aart forgot to complete”

And, don’t miss “Two stories Aart forgot to complete” by John Cooley posted on Deep Chip this week.  Click on the link to read more:  www.deepchip.com/gadfly/gad042811.html.  

More News

Products

Cadence introduced the latest version of its Allegro PCB and IC packaging technology with new capabilities that provide increased productivity and predictability across silicon, SoC and system development.  Features include improved co-design, advanced miniaturization capabilities, integrated power delivery network analysis, a DDR3 design-in kit and flexible team-design enablement to address productivity.  Cadence also announced that the Allegro 16.5 technology will be available through product configuration for users to access features on-demand for specific design tasks. 

More information at:  www.cadence.com  

Agilent Technologies released SystemVue 2011.03 software for wireless system architects and SoC designers to validate multiband, high-transistor-count wireless IC designs accurately against the latest communications standards.

 
More information at:  www.agilent.com  

Prism from CriticalBlue supports NetLogic Microsystems’ XLP, XLR and XLS multicore processor families, enabling software developers to analyze existing software applications, evaluate NetLogic Microsystems’ multicore processors and accelerate the selection and design using these multicore processors.  

More information at:  www.criticalblue.com

PLDA’s EZDMA IP solution now supports Aldec’s Riviera-PRO for Linux and Active-HDL for Windows and is available now for PCI Express Gen1 and Gen2 designs. 

More information at:  www.plda.com or www.aldec.com  

Product Adoption

SOFRADIR has implemented Asygn’s Tactyle simulator in its imager signoff flow, the final check before releasing the design for manufacture.  The simulator is used in the design of analog systems with large repetitive structures, such as large pixel arrays SOFRADIR uses to develop its infrared detector chips. 

More information at:  www.asygn.com  

HiSilicon reduced stand-by power consumption by close to 40 percent using Synopsys’ IC Compiler, a component of Synopsys’ Galaxy Implementation Platform, and deployed it in its production design flow for ICs targeting green networking applications.  HiSilicon is a leading enabler of green networks, driving toward building integrated and differentiated ASICs delivering more than 50 percent standby power savings. 

More information at:  www.synopsys.com  

IO Semiconductor Inc. selected Berkeley Design Automation’s AFS Platform for RF verification and characterization.  The Analog FastSPICE Platform is a unified verification platform for nanometer analog, RF, mixed-signal and custom digital circuits.  It combines foundry-certified nanometer SPICE accuracy, faster single-core performance than other SPICE circuit simulators, element capacity of more than 10 million and silicon-accurate device noise analysis.  The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to solve original device equations and full-circuit matrix without approximations.  It includes licenses for AFS Nano SPICE simulation, AFS circuit simulation, AFS Transient Noise Analysis, AFS RF Analysis and AFS Co-Simulation.  

More information at:  www.berkeley-da.com  

Financials

On the financial front, Cadence announced results for the first quarter of fiscal year 2011.  It reported first quarter 2011 revenue of $266 million, compared to revenue of $222 million reported for the same period in 2010.  On a GAAP basis, Cadence recognized net income of $6 million, or $0.02 per share on a diluted basis in the first quarter of 2011, compared to a net loss of $12 million, or $(0.04) per share on a diluted basis, in the same period in 2010.  Using Cadence’s non-GAAP measure, net income in the first quarter of 2011 was $23 million, or $0.09 per share on a diluted basis, as compared to net income of $6 million, or $0.02 per share on a diluted basis, in the same period in 2010. 

More information at:  www.cadence.com  

Standards Organizations

Accellera has started an IP Tagging effort to track soft IP information that will be automatically added and detectable in the final GDSII database format, and is calling for participation in its IP Tagging Technical Subcommittee.  Interested parties are invited to join and participate. 

More information at:  www.accellera.com  

The Open SystemC Initiative (OSCI) will host the first SystemC AMS Day Thursday, May 12, at the Hotel Königshof in Dresden, Germany.  It will offer a forum for system integrators, modeling experts, EDA suppliers and system-level design and verification architects and engineers to share knowledge on the industrial application and benefits of using the SystemC AMS 1.0 standard.  

More information at:  www.systemc.org/news/events/systemc_ams_day  

POLYTEDA Software Corporation is the latest member of Si2’s Design for Manufacturability Coalition (DFMC), joining Cadence Design Systems, GLOBALFOUNDRIES, IBM Corporation, Intel Corporation, Magma Design Automation, Mentor Graphics, STMicroelectronics, Synopsys, Tela Innovations and Texas Instruments.  DFMC specifies open standards for software interfaces between EDA software tools and manufacturing software, including standard terminology definitions, semantics and exchange formats for relevant manufacturing information. It also includes standard software application program interfaces (API) for models describing different manufacturing processes, yield mechanisms and circuit behaviors.  

More information at:  www.si2.org

On the Move

Oz Levia joined Jasper Design Automation as vice president of marketing and business development and corporate counsel.  Prior to joining Jasper, he was vice president of marketing and business development at SpringSoft, responsible for the development strategy of internal products and mergers and acquisitions.  Levia holds a Bachelor of Science degree and Master of Science degree in computer science from the University of Minnesota and Boston College, respectively, and a Juris Doctorate from Santa Clara University Law School. 

More information at:  www.jasper-da.com 

Check back here next Friday (May 6) for a recap of EDA news of the week.