"The manufacturing requirements at advanced process nodes, such as double-patterning lithography at 20-nanometers, are driving an industry-wide, intensive focus on newer parasitic modeling techniques to achieve signoff accuracy and performance," said Richard Trihy, director of design methodology at GLOBALFOUNDRIES. The problem is made harder to solve because the requirements are so specific to a given process methods, and not just the physics employed. Without a significant number of new standard formats and practices, design will soon become foundry dependent, significantly impacting the IP industry as well as the business practices of the semiconductor industry.

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Synopsys, Inc. collaboration with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO) has resulted in a parasitic variation modeling solution to address the effects of double patterning technology (DPT), targeted for use in 20-nanometer (nm) IC manufacturing. The new DPT model extensions will be available to the EDA and semiconductor industries through the open source licensed Interconnect Technology Format (ITF) version 2012.06 ratified by IMTAB members. The full member list is available here.

Synopsys' Interconnect Technology Format (ITF) provides detailed modeling of interconnect parasitic effects that enables designers to perform accurate parasitic extraction for timing, signal integrity, power and reliability signoff analysis. ITF offers a flexible and innovative format to accurately model the effects of increased process variation at advanced process technologies. Proven on thousands of production designs, ITF has been evolving for more than 10 years and is the semiconductor industry's most widely used interconnect modeling format. It is supported by leading semiconductor foundries, integrated device manufacturers and EDA tool providers.

Requests for ITF format enhancements come from the IMTAB membership as well as from the overall interconnect modeling format user community. Companies interested in IMTAB membership may contact IEEE-ISTO at imtab@ieee-isto.org.

The ITF format can be licensed for no charge through Synopsys' Technology Access Program (TAP-in(SM)). The latest specifications for ITF can be found at: www.synopsys.com/TapIn.

DPT is a critical technique for ensuring printability of device and interconnect layers in 20-nm IC manufacturing. However, splitting layers into two masks can introduce timing variations as a consequence of mask misalignment in the manufacturing process. To enable successful 20-nm design tapeouts and manufacturing, the IMTAB members determined that a DPT-aware modeling solution for parasitic extraction was needed to account for the timing impact and address it in the physical implementation and signoff design flow.

In addition to DPT modeling, IMTAB has also approved enhanced trench contact device modeling extensions in the ITF to include evolving 20-nm characteristics. The trench contacts are used for local device interconnections that improve density and lower resistance. However, additional challenges are introduced in modeling co-vertical conductors and associated large fringe capacitances. To deal with these issues, specific 20-nm extensions were added to explicitly model silicon dielectric underneath the device and the special dielectric region between the gate and raised diffusion to enable accurate modeling of the new parasitic effects.

"IMTAB members continue to collaborate on challenges facing the semiconductor industry in new process nodes such as 20-nanometer," said Marco Migliaro, president and CEO at IEEE-ISTO. "To improve tool interoperability around ITF modeling, IMTAB will help the industry realize a single, proven format to help speed design flows."

The next IMTAB meeting is scheduled for Tuesday, May 22, 2012. The confirmation of the date and agenda, focusing on 20nm modeling, will be posted on the IEEE-ISTO's IMTAB website: www.imtab.org.