Magma Design Automation Inc. unveiled Tekton, a new static timing analysis (STA) platform that offers significantly higher capacity and dramatically faster runtimes than traditional STA tools, without sacrificing accuracy. Unlike other solutions, Tekton runs multi-scenario analysis on low-cost hardware without requiring a large number of expensive servers and software licenses. Leveraging breakthrough technology, this revolutionary new platform addresses complex sign-off challenges and is suited for today's most challenging designs. Its next generation architecture offers the speed, capacity, and accuracy required for the industry's toughest designs. According to Rajeev Madhavan, Chairman and CEO, who announced the new product during the Magma Users Group meeting in San Jose, the new product has been engineered from scratch to meet the challenges of execution speed and accuracy presented by today's designs.

Cadence Design Systems, Inc. has released Encounter Digital Implementation (EDI) System 9.1, a complete and integrated digital design, implementation, and verification environment for the development of large-scale, complex SoCs. The new and expanded suite of capabilities in EDI System 9.1 aims to answer the industry call for improved designer productivity in developing advanced low power SoCs at leading-edge process nodes -- such as 32- and 28-nanometer -- with hundreds of millions of gates, including hundreds of IP elements and embedded processors.

Ascent Lint is the next generation lint tool in the Ascent early functional verification family of products. It performs syntax and semantic Lint checks for today's complex SoC designs. Ascent Lint 1.2 now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise.

Aldec Corporation has released its latest Design Rule Checking application, ALINT 2009.10. The product includes “best-practice” design rules for fast design closure of safety critical DO-254/ED-80 Avionics designs. ALINT 2009.10 offers a set of VHDL or Verilog design rules optimized to detect HDL code, design and verification issues including: design recoding practices, design reviews and safe synthesis guidelines. The new DO-254 design rule plug-in provides guidance to help achieve DO-254/ED-80 compliance for FPGA designs that reside within a system.