Cadence seems to be implementing its "must have" list in alphabetical order. So after Altos it was Azuro's turn. Will a B company be next? Most people in our industry will agree that clock and power optimizations are important, but what I did not know was that Cadence was doing a poor job at it. And so the company found that some key customers were going to Azuro to purchase what they could not get from Cadence. The solution was obvious: purchase the annoying interloper before a real competitor would.

A new white paper written by Dave Allen and Kiran Vittal of Atrenta

Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on their long battery lives. In wired applications, power consumption determines heat generation which in turn drives packaging costs. If not managed properly, this may have significant impact on the end appliance cost.
The landscape complicates if we also factor increasing component density of ICs, which leads to progressively increasing power density. The challenge is to pack in more while still consuming less and less power. Semiconductor industry projections indicate a 4-6x increase in leakage power for designs today and all available techniques must be applied to meet the goal that average and standby power remain flat as complexity increases.
You can read the entire paper at this location: http://www.atrenta.com/solutions_whitepaper.php

When the March edition of the Assembling The Future newsletter was published, I had no idea that Mentor, Cadence, Springsoft and Synopsys would release products that increased the level of abstraction designers could work in. It is now the turn of Synopsys to introduce a tool that allows designers to make decisions at RTL about design issues that used to be observable only later in the design process.

by Cho Moon, R&D Manager, Synopsys
Timing constraints are a crucial specification in the modern integrated circuit (IC) design flow. Implementation and signoff tools rely on them at almost every step of the design process. The rapid increase in design size and complexity, as well as the widespread reuse of intellectual property (IP) design blocks, has led to a major increase in both the extent and the complexity of timing constraints specification. Ensuring high-quality timing constraints is paramount to efficient design implementation, especially during handoffs between teams. Incomplete, inconsistent, or conflicting constraints can cause optimization and implementation tools to run ineffectively or to never converge.
In this paper, we present a unique constraint analysis technology that checks for timing constraints problems and provides an interactive environment with context-sensitive diagnostic and fixing suggestions. Using this technology, design teams can save several weeks of engineering effort in a typical IC design project.

To read this paper follow this link.