Synopsys, Inc. announced that Oticon taped out the digital signal processor (DSP) chipset for their next-generation hearing-aid devices ahead of schedule using Synopsys' Design Compiler™ Graphical RTL Synthesis, a key component of the Galaxy™ Implementation Platform. Engineers at Oticon, a world leader in the design, development and manufacture of hearing aids, needed to add new features to the next-generation DSP without increasing design area and while maintaining a very tight schedule. This was especially challenging due to the routing congestion caused by the added functionality, which could have led to multiple design iterations and a longer design schedule. To alleviate this congestion, Oticon's RTL designers deployed the congestion optimizations in Design Compiler Graphical during RTL synthesis, resulting in an easy-to-route netlist and predictable design closure ahead of schedule.
Cadence Design Systems, Inc. today announced a broadening of its existing collaboration with ARM to develop an optimized System Realization solution for ARM processors that will enable an end-to-end flow including a full set of interoperable tools, ARM® processor and physical IP, services and methodology from embedded Linux to GDSII. To accelerate adoption of this solution, Cadence will provide a full complement of tutorials and education materials including two methodology reference books and extend their ecosystem of service, methodology and training providers.
Cadence Design Systems, Inc. announced that Japanese giant Casio Computer Co. has adopted Cadence® front-end system, design, and verification technologies to develop a system LSI for digital cameras. Casio reported reduced design cycle time and improved design quality for this chip. The Casio success highlights the type of technology needed to close the "productivity gap" faced by most development teams.
To the best of my memory commercial formal tools have been around for a decade or so. Yet the Formal Verification market is still in a state of confusion, with no single tool achieving significant market superiority. There are many startups, but none has really achieve the hoped for financial success. I believe that the principal reason for this state of affair is due to the erroneous positioning of the tools.
Magma Design Automation (Nasdaq: LAVA) announced a collaborative effort with MagmaTies Partner SynTest Technologies, Inc. to integrate SynTest DFT PRO Plus products into Magma’s Talus RTL-to-GDSII IC design flow. The integration complements Magma’s scan-based DFT methodology and mutual customers have validated the flow.
The Tuesday morning Accellera breakfast at DAC has become a tradition and a test of the serious intentions of DAC attendees. After a busy Monday and an evening of intense networking showing up for breakfast at 7:30 in the morning is not easy. But many do it and they are rewarded. Not just for the food, mind you, but by the interesting panel that follows. The event will take place in room 203B of the Anaheim Convention Center and will last until 9:00 AM.
Synopsys, Inc. announced the availability of IC Compiler 2010.03, a physical implementation solution delivering up to 2.5X faster performance on multicorner/multimode (MCMM) designs, and enhanced In-Design technology for faster design closure. IC Compiler's In-Design technology helps prevent late-stage surprises by enabling signoff-accurate static timing analysis, rail analysis and physical verification during design. The new software release has production support for all known 28/32-nm design rules for major foundries, with several customer tapeouts underway.
Proving how important tools integration has become, Mentor Graphics Corporation announced the new Calibre® InRoute design and verification platform, which now enables designers to natively invoke Calibre tools within the Olympus-SoCT place and route system to achieve true manufacturing closure during physical design. The Calibre InRoute product automatically detects and fixes DRC violations and performs design for manufacturing (DFM) enhancements while optimizing for area, timing, power and signal integrity. The full power of the Olympus-SoC and Calibre platforms together improve design quality, eliminate late-stage surprises, and significantly reduce time to closure.
Some IEEE Conferences are hard to categorize; EDP and CANDE come to mind. EDP certainly isn’t a show; there are no booths or entertainment. It isn’t a workshop where someone comes in and trains the audience on a particular tool. It’s more or less a working session; where presenters come in and present their ideas, not necessarily their conclusions, and then let the audience critique their approach. This makes for a rambunctious program that comes to grips with many of the problems in electronic design today. This is a Methodologist’s Conference and marketing speak is frowned on.
Mentor Graphics Corp. has announced the availability of the HDL Designer tool's enhanced set of HDL coding checks for DO-254 compliance. This is the latest addition to Mentor's unique platform of tools that enable a requirements-driven flow from development through verification for safety-critical design.