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Design Verification and Certification

EVE Expands The Capabilities Of Its Zebu And Unveils 10-Gigabit Ethernet Validation Platform

Wed, 2012-05-16 11:18 — Gabe Moretti

EVE today announced a variety of new software to expand the capabilities of its ZeBu system-on-chip (SoC) emulation platform, including power-aware verification, post-run debugging, two vertical application validation platforms, low-power and Flash memory models, and electronic system level (ESL) tool interfaces. "Today's emulation platforms have evolved into complex verification environments to address hardware/software integration and embedded software validation of large designs," remarks Luc Burgun, EVE's chief executive officer and president.

Cadence Expands System and SoC Verification Offerings

Tue, 2012-05-15 09:38 — Gabe Moretti

The pressure to improve the verificat5ion environment is growing. Very large designs enabled by continuous advances in semiconductors manufacturing as well as the acceptance of third party IP use has increased the difficulties faced by verification engineers. Recent product releases in the emulation and acceleration market, in particular from Mentor, and virtual prototyping from Synopsys, point to increased attention on the part of EDA vendors to this market.

Cadence Design Systems, Inc is announcing a new in-circuit acceleration based on the Incisive and Palladium XP platforms for the company’s System Development Suite, extensions to the Verification IP Catalog for acceleration and emulation, and new IP targeting full system design and verification to give engineers the ability to go beyond simulation to speed verification of large-scale SoCs, sub-systems and systems.

Formal Verification: There Is An App For That

Tue, 2012-05-08 16:36 — Gabe Moretti

JasperGold from Jasper Design Automation has been one of the leading formal verification tools practically since the formal verification market was created. About a year ago Oz Levia and Rob van Blommestein joined Jasper to help with marketing. The first new product under their leadership has just been launched. As you would expect it is a bit unconventional and yet quite modern.

EVE Joins MIPI Alliance

Mon, 2012-05-07 09:02 — Gabe Moretti

The MIPI Alliance is a global, collaborative organization comprised of companies that span the mobile ecosystem committed to defining and promoting interface specifications for mobile devices. By joining the alliance, EVE will complement its family of fast ZeBu (Zero Bugs) emulation systems with synthesizable emulation verification components supporting MIPI standards.

Atrenta Ships 4.7 Release of SpyGlass Platform

Tue, 2012-05-01 15:35 — Gabe Moretti

Atrenta Inc. announced the availability of release 4.7 of its SpyGlass RTL analysis and optimization platform. Spyglass is in my opinion, the most popular front end analysis and optimization platform for digital designs.

This latest release of SpyGlass delivers automated RTL power reduction that is, on average, 2X more effective across a broad range of designs when compared to previous releases. Run-time and memory usage have also been enhanced in 4.7 – customers have reported running 280 million gate designs flat through SpyGlass in four hours.

Free Two-Week Trial of Atrenta IP Kit Available to US Customers

Wed, 2012-04-18 09:19 — Gabe Moretti

Atrenta Inc. is offering semiconductor design groups access to the Atrenta IP Kit through a free 2-week trial promotion.

Until May 31, 2012, qualified design groups in the US will be able to use Atrenta's IP Kit to perform "spring cleaning" on their third-party or internally developed IP blocks for two consecutive weeks at no cost. Atrenta's IP Kit is also used by TSMC to quality soft IP for inclusion in the TSMC 9000 IP library.

Overcoming Obstacles to ESL with a Universal Transaction-Level Model

Wed, 2012-04-04 09:28 — administrator

Yossi Veller, Mentor Graphics

The shift toward electronic system level (ESL) design and verification is beginning as the productivity of RTL modeling and verification techniques lag behind the remarkable growth of design complexity. ESL methodologies focus on the architecture of the design, raising the level of abstraction for design, modeling, and validation to the transaction level.
A transaction-level modeling (TLM) platform provides an essential framework within which many of the essential design and verification tasks can be performed. Moreover, there is a growing recognition of the advantages of extending this flow by directly synthesizing high-level abstraction code to hardware implementation; i.e., by using high-level synthesis (HLS).

STMicroelectronics Uses Via Platform To Build Custom Verification Applications

Thu, 2012-03-29 10:04 — Gabe Moretti

STMicroelectronics has successfully deployed SpringSoft's new Verdi Interoperability App (VIA) platform to implement custom verification applications for the Verdi Automated Debug System that enabled significant productivity gains within its chip development flow.

Cadence Announces New Interface VIP for Development of Cloud Infrastructure

Tue, 2012-03-27 08:20 — Gabe Moretti

Cloud computing is all the rage because it provides instant execution capabilities, availability of practically unlimited storage, and fiscal flexibility in managing computing resources. As with all systems, its acceptance and growth is based on its reliability.

Cadence Design Systems, Inc. is adding support for two popular protocol standards used in cloud computing applications, 12Gb/s SAS and NVM Express, to the Cadence Verification IP (VIP) Catalog.

Cadence Delivers IP Supporting LPDDR3 Memory Standard

Thu, 2012-03-22 17:13 — administrator

Cadence Design Systems, Inc. announced the addition of design intellectual property (IP) for the LPDDR3 mobile memory standard to the company's design IP portfolio. Designed to provide the high bandwidth and low power consumption required by smartphones and tablets, the Cadence LPDDR3 memory IP solution includes integrated controller and PHY support, virtual prototyping, verification IP and Allegro design-in kits to accelerate implementation and reduce design risk.