Real Intent, Inc. announced version 2.0 of its Ascent Lint tool for early functional verification. It adds 60 comprehensive rules including new FSM checks, while maintaining its analysis speed of up to 450M gates in less than one hour, with no need for hierarchical processing. Real Intent also added Verdi3 support for integration to this industry-leading debug platform from Synopsys.
Increasing design complexity is posing heighten verification complexity. Most of the consumer electronic products that are pushing vendors toward state of the art processes require real time responses. These applications cannot be debugged using software based tools. Thus the use of FPGAs for SoC verification has become the norm.
In the last two weeks both Synopsys and Tektronix have introduced new powerful verification solutions to aid engineers developing SoC devices.
One of the greatest values of a User Group is the ability to network with other users and compare the methods used with various tools from the vendor. The Jasper Users Group meeting will be held on November 12 and 13 at the Cypress Hotel in Cupertino, CA. The gathering will be especially interesting to designers, verification engineers and engineering managers. Attendees from around the world to share the latest verification best practices.
Jasper design Automation will hold its 2012 Users Group meeting at the Cypress Hotel in Cupertino on November 12 and 13. Jasper’s annual user meeting will gather designers, verification engineers and engineering managers from around the world to share the latest verification best practices. Jasper’s User Group meeting is an interactive, in-depth technical conference, which focuses on the needs of the Jasper Design Automation user community with the primary goal being to deliver immediately useful technical content.
Mentor Graphics Corporation has updated its Universal Verification Methodology Connect (UVM Connect) to bring the benefits of it to the Open Verification Methodology (OVM) community. UVM Connect has been extended to allow it to be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With UVM Connect 2.2, teams using OVM can connect with SystemC models and other environments as well.
Title: When to Retool the Front-End Design Flow?
By Rick Eram, Director of Sales and Field Operations at Real Intent
Just after Synopsys acquired Virage Logic a few companies declared that the purchase would put Synopsys in direct competition with ARM and thus that the account was ripe for the taking. Any intelligent industry analyst, there might be a few remaining, would have immediately seen that the ARC core is not a direct competitor of the ARM family of products. But anything is a good source of rumor, and an opportunity to generate words that enable advertising revenue. Before I go on, I must confess that I am a bit puzzled by the lukewarm efforts made by Synopsys in inserting marketing and sales strength in the ARC product, but then again this is probably one reason that Aart chose Chi-Foon and not me as a co-CEO.
Synopsys, Inc. announced the launch of VIP-Central.org, the first industry-wide, technical community site focused on system-on-chip (SoC) verification engineers and users of verification IP (VIP). It provides a centralized online resource of relevant forums and blogs focusing on verification of today's industry-standard protocols. Visit VIP-Central.org online at http://www.vip-central.org/.
Zuken announced the immediate availability of version 14 of CR-5000, its advanced PCB and IC Package design software. The new version offers a number of significant productivity enhancements for greater collaboration in FPGA development and for high-speed design. Many enhancements have also been included in CR-5000 Lightning, Zuken’s leading high-speed design verification tool that enables rapid, accurate results, coupled with first-rate signal integrity, EMC and power integrity analysis.
A few days before DAC Calypto announced Catapult Low-Power (LP), a high-level synthesis (HLS) tool that adds power as an optimization goal. Since August 2011, when Calypto received Catapult C from Mentor the company has integrated the tool within the ESL flow that includes SLEC, its equivalence checking tool, and now has also integrated a power analysis and evaluation function into the tool renamed simply Catapult.