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Design Verification and Certification

Springsoft Unveils New VIA Exchange For Verdi

Tue, 2011-10-04 09:38 — Gabe Moretti

SpringSoft, Inc. launched the Verdi Interoperability Apps (VIA) Exchange, an open platform for creating and sharing custom applications deployed with SpringSoft’s Verdi Automated Debug System. The VIA Exchange consists of the newly productized application programming interface (API) to SpringSoft’s de facto standard databases and the www.via-exchange.com website for download of the VIA interface, scripting tools and command libraries that can be used to create customizable Verdi scripts and utilities. VIA Exchange users can also submit scripts or end use applications to the exchange.

Congestion Mitigation During RTL Development

Fri, 2011-07-29 09:56 — Gabe Moretti

A new whitepaper from Atrenta that reiterates the importance of early analysis and correction of layout problems before place and route produces issues that are more costly to address.

Facilitating At-Speed Test At The Register Transfer Level

Wed, 2011-06-29 07:26 — Gabe Moretti

Dr. Ralph Marlett and Kiran Vittal of Atrenta have written a paper proposing a solution to a common DFT problem. The paper is available by visiting this site. Once there select the paper from the list by clicking on the title.

ARM Chooses Jasper For Validation Methodology Upgrade

Fri, 2011-05-27 08:51 — Gabe Moretti

ARM has completed a deployment of Jasper technology and solutions that enhances the validation methodology for ARM® AMBA® protocol-based processor and system IP. The adoption enables design and validation teams at ARM to address a wide range of verification issues such as the absence of deadlocks, cache coherency, x-propagation detection, control register verification, and protocol certification. This is a significant sign of the worth of Jasper technology and products usability. It is very important to ARM to support its IP products with the best tools available on the market.

Cadence Announces "App-driven" System Development Flow

Wed, 2011-05-04 06:39 — Gabe Moretti

The new flow is a direct result of the EDA360 vision published just about one year ago. The document recognizes that systems are designed and developed based on the application they provide, not on the latest capabilities of hardware manufacturing. hardware and software components are chosen given the requirements of the application, and in the majority of cases, the software components demand the majority of the development effort, and thus are responsible for the larger share of the cost.

Verisilicon Standardizes On Springsoft's Verdi Debug Platform

Tue, 2011-04-19 13:03 — Gabe Moretti

SpringSoft, Inc. has announced that VeriSilicon Holdings Co. Ltd. has selected its Verdi Automated Debug System as the standard debug platform. The Verdi software is currently being deployed by VeriSilicon's worldwide research and development (R&D) organization and implemented in its debug reference flow to significantly reduce debug time and accelerate functional verification of complex digital IC and system-on-chip (SoC) designs at advanced technology nodes.

Springsoft Integrates Verdi with DFTView from Source III

Mon, 2011-03-28 07:42 — Gabe Moretti

SpringSoft, Inc. and Source III, Inc. have announced the availability of Source III’s new DFTView™ tool and its integration with SpringSoft’s Verdi™ Automated Debug System. Using the products together, DFT and test Engineers are able to graphically view and debug the contents of industry standard test files in the WGL and STIL formats. This integration not only expands the power of Verdi but also makes it available to a wider set of users.

SI training classes from Bogatin Enterprises coming to Santa Clara and Asia

Wed, 2011-03-23 09:18 — administrator

Eric Bogatin's signal integrity training classes have started off with a bang this year. The three new classes in our High Speed Serial Link series, sold out in their first public offering. The hands on labs with each class have been a huge hit.

Aldec Ensures That Its Simulators Work With CAST IP

Thu, 2011-03-10 09:23 — Gabe Moretti

Aldec, Inc. has partnered with CAST to ensure that CAST’s IP cores are compatible with Aldec’s suite of design verification tools.
This means that ASIC and FPGA designers using Aldec’s Riviera-PRO or Active-HDL simulators with CAST’s IP cores can count on a smooth design and verification experience. CAST is also now a member of Aldec’s Unite IP partner program.

Springsoft's Siloti And Verdi Play Together

Sat, 2011-03-05 09:31 — Gabe Moretti

SpringSoft, Inc. has integrated an enhanced version of its Siloti™ Visibility Automation System with the Verdi™ Automated Debug System. Siloti now offers a streamlined, easy-to-use flow for system-on-chip (SoC) verification and debug. The latest software release incorporates a new reusable behavior analysis database to eliminate redundant analysis cycles and speed up design preparation time by at least 10X over previous releases during debug operations.