Magma Design Automation announced the availability of a new release of the Titan Analog/Mixed-Signal (Titan AMS) Design Platform. With patent-pending analog design technology, Titan provides an innovative FlexCell-to-GDSII analog/mixed-signal (AMS) flow that organically integrates both electrical design and physical design into one unified design methodology. More than 30 customers, including the majority of the top 20 semiconductor companies in the world have adopted Titan AMS, according to Magma.

Magma® Design Automation Inc. announced that iWatt has adopted the Titan™ platform to improve analog design and layout productivity, and to automate difficult routing tasks including analog cell layouts and chip-level assembly. iWatt, a developer of energy-efficient digital power supply control integrated circuits (ICs) used in leading-edge power supplies, adopted Titan based on results of an extensive evaluation in which Titan enabled iWatt’s designers to set up and route a design in just 2 days – an effort that would have taken more than 2 weeks to do manually.

Mentor Graphics Corporation announced the new Calibre® RealTime platform for signoff-quality physical verification during design creation. The first release provides instantaneous design rule checking (DRC) in the SpringSoft Laker™ custom IC design and layout solution, using the same Calibre decks as the signoff flow. A version for the Mentor® IC Station® custom design environment will be available in June.

Cadence Design Systems, Inc announced major enhancements to its Virtuoso®-based custom/analog flow, boosting productivity across the entire flow from initial design specification to final GDSII and for process nodes down to 20 nanometers. The expanded custom/analog flow -- spanning design, implementation, and verification -- includes methodology improvements to help designers manage design parasitics, a DFM capability integrated within the Virtuoso environment, and the integrated Virtuoso Power System, which provides a signoff-accurate way to manage power and signal integrity issues. These enhancements, and many more, are aimed at boosting designer productivity across all process nodes.