Gabe on EDA

Mentor Graphics Corp. announced that the Catapult C Synthesis tool has been extended to support control logic and manage low power design requirements, thus enabling full-chip high-level synthesis.

Altera Corporation announced a new low-power FPGA family with security features. The Cyclone III LS FPGAs offer high logic, memory, and DSP density per board area. The Cyclone III LS FPGAs, which are shipping now, target power and board-space-sensitive applications in all market segments including military and industrial.

The Open Virtual Platform (OVP) initiative (www.OVPworld.org), founded by Imperas with the help of 18 companies and individuals from the embedded systems user community, processor intellectual property developers, electronic design automation, service providers and academia, has celebrated its one year anniversary.

I’ve been on the executive committee for both DAC and ICCAD, and the same question keeps coming up: What can we do as a conference to create ties to the embedded software world?
This year, I decided that it was time to do something about it. After some probing, I realized the difficulty of the task. Seriously, how many software developers make it to DAC?

Zocalo Tech, Inc. has released is Zazz. The purpose of the product is to make using assertion libraries quick, easy and accurate by automating error prone tasks using a Graphical User Interface (GUI). With Zazz, the checkers from the most widely used assertion libraries can be attached to a design and documented.

Calypto Design Systems Inc. announced the availability of its PowerPro MG (memory gating) tool. The new tool automatically generates power-optimized RTL by taking advantage of the low-power modes available in today’s leading on-chip memories.

Following my article on the decision by Cadence to leave the DFM market segment, I received an email from a Cadence employee that has asked to be anonymous because "I'm sharing confidential internal information here." He disputes the conclusion Gary Smith, other editors, analysts, and myself, arrived to based on the contents of the Cadence press release of June 10th.

Gary Smith wrote a short but insightful piece on the decision by Cadence to leave the DFM market. (http://www.garysmitheda.com/note-Cadence-layoff.html). The bottom line of Gary's analysis is that the decision is a strategic mistake. My question is: is it really an oversight?

CoWare Inc. announced the availability of a new Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect, enabling early and efficient optimization of next-generation system-on-chip (SoC) architectures using ARM® AMBA®-based virtual platforms.

Synopsys, Inc. has released new advanced analog simulation and layout capabilities in its Galaxy Custom Designer implementation solution.