Evatronix SA, announced a series of free technical seminars on two of the most popular IP technologies – 8051 and USB – taking place in China and Taiwan – Beijing (March 25) and Hsinchu (March 30), respectively.

"We are excited about this opportunity to share the 13 years of our IP design and integration experience with every engineer involved in the SoC development process," said Michal Jedrak, Technical Marketing Manager at Evatronix. "Our seminars offer an excellent chance to discuss the hottest ASIC and FPGA design topics and get immediate answers to key questions."

Magma Design Automation Inc. announced the availability of FineSim Fast Monte Carlo, a technology the company labels a revolutionary new alternative to traditional Monte Carlo analysis. Most engineers rely heavily on statistical methods such as traditional Monte Carlo analysis for design reliability, an approach that has limitations making accurate analysis almost impossible. FineSim Fast Monte Carlo uses proprietary dynamic error-controlled algorithms along with statistical techniques to provide dramatic improvement in speed and accuracy compared to traditional Monte Carlo statistical analysis. It has shown as much as 100 times better runtime when compared to other commercial methods, with superior accuracy.

Magma Design Automation Inc. unveiled Tekton, a new static timing analysis (STA) platform that offers significantly higher capacity and dramatically faster runtimes than traditional STA tools, without sacrificing accuracy. Unlike other solutions, Tekton runs multi-scenario analysis on low-cost hardware without requiring a large number of expensive servers and software licenses. Leveraging breakthrough technology, this revolutionary new platform addresses complex sign-off challenges and is suited for today's most challenging designs. Its next generation architecture offers the speed, capacity, and accuracy required for the industry's toughest designs. According to Rajeev Madhavan, Chairman and CEO, who announced the new product during the Magma Users Group meeting in San Jose, the new product has been engineered from scratch to meet the challenges of execution speed and accuracy presented by today's designs.

GateRocket Inc. has significantly bolstered its technical, marketing, and sales acumen with the addition of two savvy and experienced chip design industry veterans. Jim Hogan, well-known EDA entrepreneur, investor, and executive has joined the GateRocket Advisory board; and Jim Wagner, with extensive EDA sales experience, has been named GateRocket Director of Sales.

Carbon Design Systems announced the availability of virtual models for ARM Mali Graphic Processor Units (GPUs). These new models, including the Mali-200 and Mali-400MP, are compiled directly from the ARM register transfer level (RTL) code and are 100% implementation accurate.

The Open SystemC Initiative (OSCI) has released the SystemC Analog/Mixed-signal (AMS) extensions language standard, AMS 1.0. The AMS 1.0 standard is the first modeling language targeting system-level design and verification to describe analog/mixed-signal behavior as natural extension to existing SystemC-based design methodologies.

Forte Design Systems, announced it is shipping the latest version of CellMath Designer datapath synthesis and Cellmath IP software. The CellMath family allows register transfer level (RTL) designers to reduce area, improve performance and lower power consumption for their existing datapath-intensive design blocks.

Real Intent Inc. announced that it is shipping Meridian Clock Domain Crossing (CDC) verification software Version 3.0. The company believes that Meridian CDC is the most precise and comprehensive CDC solution in the market today. It employs a multi-strategy analysis approach including Automatic Clock Intent Analysis, Formal Analysis, Hierarchical Analysis, and Dynamic Analysis (SimPortal).

AgO Inc. has introduced AnXplorer -- a new tool for optimizing analog and RF circuits. Starting with an unsized SPICE netlist, variables for device dimensions and a set of design objectives and constraints, AnXplorer optimizes device sizes by rigorously exploring the design space. By centering the design across all specified, process, temperature and voltage corners, AnXplorer achieves a robust design thereby enhancing the yield and improving the probability of first time silicon success.

Jay Vleeschhouwer authors a weekly research paper on the software industry. This week he covered both Cadence and Magma among other companies that do not serve the EDA industry. Some of the remarks about Cadence will sound familiar to those who either attended the EDAC CEO Panel, or Lip-Bu Tan's keynote speech at DVCon.